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79d16e4540
Only some Soc need Schmitter feature, so move the implementation into their own files. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
328 lines
7.5 KiB
C
328 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
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{
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.num = 2,
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.pin = 12,
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.reg = 0x24,
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.bit = 8,
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.mask = 0x3
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}, {
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.num = 2,
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.pin = 15,
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.reg = 0x28,
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.bit = 0,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 23,
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.reg = 0x30,
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.bit = 14,
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.mask = 0x3
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},
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};
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static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
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{
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/* uart2dbg_rxm0 */
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.bank_num = 1,
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.pin = 1,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16) | BIT(16 + 1),
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}, {
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/* uart2dbg_rxm1 */
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.bank_num = 2,
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.pin = 1,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16) | BIT(16 + 1) | BIT(0),
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}, {
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/* gmac-m1_rxd0 */
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.bank_num = 1,
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.pin = 11,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 2) | BIT(2),
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}, {
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/* gmac-m1-optimized_rxd3 */
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.bank_num = 1,
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.pin = 14,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 10) | BIT(10),
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}, {
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/* pdm_sdi0m0 */
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.bank_num = 2,
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.pin = 19,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 3),
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}, {
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/* pdm_sdi0m1 */
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.bank_num = 1,
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.pin = 23,
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.func = 3,
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.route_offset = 0x50,
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.route_val = BIT(16 + 3) | BIT(3),
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}, {
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/* spi_rxdm2 */
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.bank_num = 3,
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.pin = 2,
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.func = 4,
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.route_offset = 0x50,
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.route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
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}, {
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/* i2s2_sdim0 */
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.bank_num = 1,
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.pin = 24,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16 + 6),
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}, {
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/* i2s2_sdim1 */
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.bank_num = 3,
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.pin = 2,
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.func = 6,
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.route_offset = 0x50,
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.route_val = BIT(16 + 6) | BIT(6),
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}, {
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/* card_iom1 */
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.bank_num = 2,
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.pin = 22,
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.func = 3,
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.route_offset = 0x50,
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.route_val = BIT(16 + 7) | BIT(7),
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}, {
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/* tsp_d5m1 */
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.bank_num = 2,
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.pin = 16,
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.func = 3,
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.route_offset = 0x50,
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.route_val = BIT(16 + 8) | BIT(8),
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}, {
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/* cif_data5m1 */
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.bank_num = 2,
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.pin = 16,
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.func = 4,
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.route_offset = 0x50,
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.route_val = BIT(16 + 9) | BIT(9),
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},
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};
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static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data, route_reg, route_val;
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regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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? priv->regmap_pmu : priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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if (bank->route_mask & BIT(pin)) {
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if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
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&route_val)) {
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ret = regmap_write(regmap, route_reg, route_val);
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if (ret)
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return ret;
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}
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}
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3328_PULL_OFFSET 0x100
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static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3328_PULL_OFFSET;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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}
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static int rk3328_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -ENOTSUPP;
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rk3328_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3328_DRV_GRF_OFFSET 0x200
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static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3328_DRV_GRF_OFFSET;
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*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
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*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
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}
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static int rk3328_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data;
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u8 bit;
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int type = bank->drv[pin_num / 8].drv_type;
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rk3328_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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ret = rockchip_translate_drive_value(type, strength);
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if (ret < 0) {
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debug("unsupported driver strength %d\n", strength);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3328_SCHMITT_BITS_PER_PIN 1
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#define RK3328_SCHMITT_PINS_PER_REG 16
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#define RK3328_SCHMITT_BANK_STRIDE 8
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#define RK3328_SCHMITT_GRF_OFFSET 0x380
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static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3328_SCHMITT_GRF_OFFSET;
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*reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
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*reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
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*bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
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return 0;
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}
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static int rk3328_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg;
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u8 bit;
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u32 data;
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rk3328_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = BIT(bit + 16) | (enable << bit);
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return regmap_write(regmap, reg, data);
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}
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static struct rockchip_pin_bank rk3328_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
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IOMUX_WIDTH_3BIT,
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IOMUX_WIDTH_3BIT,
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0),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
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IOMUX_WIDTH_3BIT,
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IOMUX_WIDTH_3BIT,
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0,
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0),
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};
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static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
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.pin_banks = rk3328_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
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.grf_mux_offset = 0x0,
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.iomux_recalced = rk3328_mux_recalced_data,
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.niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
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.iomux_routes = rk3328_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
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.set_mux = rk3328_set_mux,
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.set_pull = rk3328_set_pull,
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.set_drive = rk3328_set_drive,
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.set_schmitt = rk3328_set_schmitt,
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};
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static const struct udevice_id rk3328_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3328-pinctrl",
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.data = (ulong)&rk3328_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3328) = {
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.name = "rockchip_rk3328_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3328_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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