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https://github.com/AsahiLinux/u-boot
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cae39ae365
Microblaze is storing reset vector at address 0x0. It means soft reset can be done by just jumping to this address. This code was in platform code but sysreset interface is providing enough capabilities to have more options how to reset the system. It can go from gpio reset through watchdog reset till soft reset. The driver has not compatible string because this is cpu specific and DM core is not able to detect compatible string in DT root that's why this driver will be instantiated from platform code by calling device_bind_driver(gd->dm_root, "mb_soft_reset", "reset_soft", NULL); It should be bind as the last reset method to ensure that hw reset is called before this. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
15 lines
620 B
Makefile
15 lines
620 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2016 Cadence Design Systems Inc.
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obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
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obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
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obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
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obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
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obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
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obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
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obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
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obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
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obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
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obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
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obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
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