mirror of
https://github.com/AsahiLinux/u-boot
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caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
255 lines
6.2 KiB
C
255 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/immap_83xx.h>
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#if defined(CONFIG_PINCTRL)
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/pinctrl.h>
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#include <linux/ioport.h>
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/**
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* struct qe_io_platdata
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*
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* @base: Base register address
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* @num_par_io_ports number of io ports
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*/
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struct qe_io_platdata {
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qepio83xx_t *base;
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u32 num_io_ports;
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};
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#endif
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#define NUM_OF_PINS 32
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/** qe_cfg_iopin configure one io pin setting
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*
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* @par_io: pointer to parallel I/O base
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* @port: io pin port
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* @pin: io pin number which get configured
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* @dir: direction of io pin 2 bits valid
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* 00 = pin disabled
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* 01 = output
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* 10 = input
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* 11 = pin is I/O
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* @open_drain: is pin open drain
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* @assign: pin assignment registers select the function of the pin
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*/
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static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
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int open_drain, int assign)
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{
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u32 dbit_mask;
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u32 dbit_dir;
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u32 dbit_asgn;
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u32 bit_mask;
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u32 tmp_val;
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int offset;
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offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
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/* Calculate pin location and 2bit mask and dir */
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dbit_mask = (u32)(0x3 << offset);
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dbit_dir = (u32)(dir << offset);
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/* Setup the direction */
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tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
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in_be32(&par_io->ioport[port].dir2) :
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in_be32(&par_io->ioport[port].dir1);
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if (pin > (NUM_OF_PINS / 2) - 1) {
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out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
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} else {
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out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
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}
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/* Calculate pin location for 1bit mask */
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bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
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/* Setup the open drain */
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tmp_val = in_be32(&par_io->ioport[port].podr);
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if (open_drain)
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out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
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else
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out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
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/* Setup the assignment */
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tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
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in_be32(&par_io->ioport[port].ppar2) :
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in_be32(&par_io->ioport[port].ppar1);
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dbit_asgn = (u32)(assign << offset);
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/* Clear and set 2 bits mask */
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if (pin > (NUM_OF_PINS / 2) - 1) {
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out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
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} else {
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out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
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}
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}
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#if !defined(CONFIG_PINCTRL)
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/** qe_config_iopin configure one io pin setting
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*
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* @port: io pin port
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* @pin: io pin number which get configured
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* @dir: direction of io pin 2 bits valid
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* 00 = pin disabled
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* 01 = output
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* 10 = input
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* 11 = pin is I/O
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* @open_drain: is pin open drain
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* @assign: pin assignment registers select the function of the pin
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*/
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void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
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qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
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}
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#else
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static int qe_io_ofdata_to_platdata(struct udevice *dev)
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{
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struct qe_io_platdata *plat = dev->plat;
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fdt_addr_t addr;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->base = (qepio83xx_t *)addr;
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if (dev_read_u32(dev, "num-ports", &plat->num_io_ports))
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return -EINVAL;
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return 0;
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}
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/**
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* par_io_of_config_node config
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* @dev: pointer to pinctrl device
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* @pio: ofnode of pinconfig property
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*/
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static int par_io_of_config_node(struct udevice *dev, ofnode pio)
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{
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struct qe_io_platdata *plat = dev->plat;
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qepio83xx_t *par_io = plat->base;
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const unsigned int *pio_map;
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int pio_map_len;
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pio_map = ofnode_get_property(pio, "pio-map", &pio_map_len);
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if (!pio_map)
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return -ENOENT;
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pio_map_len /= sizeof(unsigned int);
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if ((pio_map_len % 6) != 0) {
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dev_err(dev, "%s: pio-map format wrong!\n", __func__);
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return -EINVAL;
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}
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while (pio_map_len > 0) {
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/*
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* column pio_map[5] from linux (has_irq) not
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* supported in u-boot yet.
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*/
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qe_cfg_iopin(par_io, (u8)pio_map[0], (u8)pio_map[1],
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(int)pio_map[2], (int)pio_map[3],
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(int)pio_map[4]);
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pio_map += 6;
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pio_map_len -= 6;
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}
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return 0;
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}
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int par_io_of_config(struct udevice *dev)
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{
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u32 phandle;
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ofnode pio;
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int err;
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err = ofnode_read_u32(dev_ofnode(dev), "pio-handle", &phandle);
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if (err) {
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dev_err(dev, "%s: pio-handle not available\n", __func__);
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return err;
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}
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pio = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(pio)) {
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dev_err(dev, "%s: unable to find node\n", __func__);
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return -EINVAL;
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}
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/* To Do: find pinctrl device and pass it */
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return par_io_of_config_node(NULL, pio);
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}
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/*
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* This is not nice!
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* pinsettings should work with "pinctrl-" properties.
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* Unfortunately on mpc83xx powerpc linux device trees
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* devices handle this with "pio-handle" properties ...
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*
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* Even worser, old board code inits all par_io
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* pins in one step, if U-Boot uses the device
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* or not. So init all par_io definitions here too
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* as linux does this also.
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*/
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static void config_qe_ioports(struct udevice *dev)
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{
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ofnode ofn;
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for (ofn = dev_read_first_subnode(dev); ofnode_valid(ofn);
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ofn = dev_read_next_subnode(ofn)) {
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/*
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* ignore errors here, as may the subnode
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* has no pio-handle
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*/
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par_io_of_config_node(dev, ofn);
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}
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}
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static int par_io_pinctrl_probe(struct udevice *dev)
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{
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config_qe_ioports(dev);
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return 0;
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}
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static int par_io_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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return 0;
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}
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const struct pinctrl_ops par_io_pinctrl_ops = {
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.set_state = par_io_pinctrl_set_state,
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};
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static const struct udevice_id par_io_pinctrl_match[] = {
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{ .compatible = "fsl,mpc8360-par_io"},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(par_io_pinctrl) = {
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.name = "par-io-pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = of_match_ptr(par_io_pinctrl_match),
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.probe = par_io_pinctrl_probe,
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.ofdata_to_platdata = qe_io_ofdata_to_platdata,
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.plat_auto = sizeof(struct qe_io_platdata),
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.ops = &par_io_pinctrl_ops,
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#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
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.flags = DM_FLAG_PRE_RELOC,
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#endif
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};
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#endif
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