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35fe948e3b
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
96 lines
3.3 KiB
C
96 lines
3.3 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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static u32 serdes1_prtcl_map;
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static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0] = {NONE, NONE, NONE, NONE},
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[1] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[2] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[3] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[4] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[5] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
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[12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[22] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[23] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[24] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[25] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[26] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
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[33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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[44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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[45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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[46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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[47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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};
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int is_serdes_configured(enum srds_prtcl prtcl)
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{
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return (1 << prtcl) & serdes1_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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int lane;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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}
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