Ye Li dc77d0f9fc imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock ... The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready. And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>		2022-02-05 13:38:39 +01:00
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asm	imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock	2022-02-05 13:38:39 +01:00
debug	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00