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u-boot/arch/riscv
Torsten Duwe 6164d86984 riscv: jh7110: enable riscv,timer in the device tree
The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
Note that in the device tree.

Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:36 +08:00
..
cpu riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback 2023-08-22 08:07:54 -06:00
dts riscv: jh7110: enable riscv,timer in the device tree 2023-09-05 10:53:36 +08:00
include/asm cmd/sbi: display new extensions 2023-08-10 10:57:56 +08:00
lib riscv: Rename SiFive CLINT to RISC-V ALINT 2023-07-12 13:21:40 +08:00
config.mk riscv: Support CONFIG_REMAKE_ELF 2023-04-20 20:45:08 +08:00
Kconfig riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE 2023-08-10 10:58:12 +08:00
Makefile riscv: support building double-float modules 2022-10-20 15:22:21 +08:00