mirror of
https://github.com/AsahiLinux/u-boot
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9e75875849
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
203 lines
5.8 KiB
C
203 lines
5.8 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#ifdef CONFIG_SYS_DPAA_QBMAN
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struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
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/* dqrr liodn, frame data liodn, liodn off, sdest */
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SET_QP_INFO(1, 27, 1, 0),
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SET_QP_INFO(2, 28, 1, 0),
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SET_QP_INFO(3, 29, 1, 1),
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SET_QP_INFO(4, 30, 1, 1),
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SET_QP_INFO(5, 31, 1, 2),
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SET_QP_INFO(6, 32, 1, 2),
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SET_QP_INFO(7, 33, 1, 3),
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SET_QP_INFO(8, 34, 1, 3),
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SET_QP_INFO(9, 35, 1, 4),
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SET_QP_INFO(10, 36, 1, 4),
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SET_QP_INFO(11, 37, 1, 5),
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SET_QP_INFO(12, 38, 1, 5),
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SET_QP_INFO(13, 39, 1, 6),
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SET_QP_INFO(14, 40, 1, 6),
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SET_QP_INFO(15, 41, 1, 7),
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SET_QP_INFO(16, 42, 1, 7),
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SET_QP_INFO(17, 43, 1, 8),
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SET_QP_INFO(18, 44, 1, 8),
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SET_QP_INFO(19, 45, 1, 9),
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SET_QP_INFO(20, 46, 1, 9),
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SET_QP_INFO(21, 47, 1, 10),
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SET_QP_INFO(22, 48, 1, 10),
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SET_QP_INFO(23, 49, 1, 11),
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SET_QP_INFO(24, 50, 1, 11),
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SET_QP_INFO(65, 89, 1, 0),
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SET_QP_INFO(66, 90, 1, 0),
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SET_QP_INFO(67, 91, 1, 1),
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SET_QP_INFO(68, 92, 1, 1),
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SET_QP_INFO(69, 93, 1, 2),
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SET_QP_INFO(70, 94, 1, 2),
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SET_QP_INFO(71, 95, 1, 3),
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SET_QP_INFO(72, 96, 1, 3),
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SET_QP_INFO(73, 97, 1, 4),
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SET_QP_INFO(74, 98, 1, 4),
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SET_QP_INFO(75, 99, 1, 5),
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SET_QP_INFO(76, 100, 1, 5),
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SET_QP_INFO(77, 101, 1, 6),
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SET_QP_INFO(78, 102, 1, 6),
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SET_QP_INFO(79, 103, 1, 7),
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SET_QP_INFO(80, 104, 1, 7),
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SET_QP_INFO(81, 105, 1, 8),
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SET_QP_INFO(82, 106, 1, 8),
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SET_QP_INFO(83, 107, 1, 9),
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SET_QP_INFO(84, 108, 1, 9),
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SET_QP_INFO(85, 109, 1, 10),
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SET_QP_INFO(86, 110, 1, 10),
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SET_QP_INFO(87, 111, 1, 11),
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SET_QP_INFO(88, 112, 1, 11),
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SET_QP_INFO(25, 51, 1, 0),
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SET_QP_INFO(26, 52, 1, 0),
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};
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#endif
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struct srio_liodn_id_table srio_liodn_tbl[] = {
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SET_SRIO_LIODN_1(1, 307),
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SET_SRIO_LIODN_1(2, 387),
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};
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int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
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struct liodn_id_table liodn_tbl[] = {
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#ifdef CONFIG_SYS_DPAA_QBMAN
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SET_QMAN_LIODN(62),
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SET_BMAN_LIODN(63),
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#endif
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SET_SDHC_LIODN(1, 552),
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SET_PME_LIODN(117),
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SET_USB_LIODN(1, "fsl-usb2-mph", 553),
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SET_USB_LIODN(2, "fsl-usb2-dr", 554),
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SET_SATA_LIODN(1, 555),
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SET_SATA_LIODN(2, 556),
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SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
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SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
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SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
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SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
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SET_DMA_LIODN(1, 147),
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SET_DMA_LIODN(2, 227),
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SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
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SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
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SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
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SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
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#ifdef CONFIG_SYS_PMAN
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SET_PMAN_LIODN(1, 513),
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SET_PMAN_LIODN(2, 514),
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SET_PMAN_LIODN(3, 515),
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#endif
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/* SET_NEXUS_LIODN(557), -- not yet implemented */
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};
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int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
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#ifdef CONFIG_SYS_DPAA_FMAN
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struct liodn_id_table fman1_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(1, 0, 88),
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SET_FMAN_RX_1G_LIODN(1, 1, 89),
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SET_FMAN_RX_1G_LIODN(1, 2, 90),
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SET_FMAN_RX_1G_LIODN(1, 3, 91),
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SET_FMAN_RX_1G_LIODN(1, 4, 92),
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SET_FMAN_RX_1G_LIODN(1, 5, 93),
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SET_FMAN_RX_10G_LIODN(1, 0, 94),
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SET_FMAN_RX_10G_LIODN(1, 1, 95),
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};
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int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
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#if (CONFIG_SYS_NUM_FMAN == 2)
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struct liodn_id_table fman2_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(2, 0, 88),
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SET_FMAN_RX_1G_LIODN(2, 1, 89),
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SET_FMAN_RX_1G_LIODN(2, 2, 90),
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SET_FMAN_RX_1G_LIODN(2, 3, 91),
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SET_FMAN_RX_1G_LIODN(2, 4, 92),
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SET_FMAN_RX_1G_LIODN(2, 5, 93),
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SET_FMAN_RX_10G_LIODN(2, 0, 94),
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SET_FMAN_RX_10G_LIODN(2, 1, 95),
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};
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int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
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#endif
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#endif
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struct liodn_id_table sec_liodn_tbl[] = {
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SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
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SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
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SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
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SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
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SET_SEC_RTIC_LIODN_ENTRY(a, 453),
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SET_SEC_RTIC_LIODN_ENTRY(b, 549),
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SET_SEC_RTIC_LIODN_ENTRY(c, 550),
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SET_SEC_RTIC_LIODN_ENTRY(d, 551),
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SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
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SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
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SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
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SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
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SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
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SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
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SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
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SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
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};
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int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
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#ifdef CONFIG_SYS_DPAA_RMAN
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struct liodn_id_table rman_liodn_tbl[] = {
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/* Set RMan block 0-3 liodn offset */
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SET_RMAN_LIODN(0, 678),
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SET_RMAN_LIODN(1, 679),
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SET_RMAN_LIODN(2, 680),
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SET_RMAN_LIODN(3, 681),
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};
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int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
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#endif
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struct liodn_id_table liodn_bases[] = {
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#ifdef CONFIG_SYS_DPAA_DCE
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[FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694),
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#endif
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[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
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#ifdef CONFIG_SYS_DPAA_FMAN
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[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
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#if (CONFIG_SYS_NUM_FMAN == 2)
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[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069),
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#endif
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
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#endif
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#ifdef CONFIG_SYS_DPAA_RMAN
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[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
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#endif
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};
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