u-boot/arch/riscv/cpu/nx25/cpu.c
Rick Chen e8e39597a3 riscv: cpu: Add nx25 to support RISC-V
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch

Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.

Detail verification message please see doc/README.ae250.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12 08:05:12 -05:00

33 lines
663 B
C

/*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* CPU specific code */
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
/*
* cleanup_before_linux() is called just before we call linux
* it prepares the processor for linux
*
* we disable interrupt and caches.
*/
int cleanup_before_linux(void)
{
disable_interrupts();
/* turn off I/D-cache */
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
panic("nx25-ae250 wdt not support yet.\n");
}