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https://github.com/AsahiLinux/u-boot
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d13de4faaf
Add a DM reset driver for StarFive JH7110 SoC. Note that the register base address of reset controller is the same with the clock controller. Therefore, there is no device tree node alone for reset driver.It binds device node in the clock driver Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
35 lines
1.4 KiB
Makefile
35 lines
1.4 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Copyright (c) 2016, NVIDIA CORPORATION.
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#
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obj-$(CONFIG_DM_RESET) += reset-uclass.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
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obj-$(CONFIG_STI_RESET) += sti-reset.o
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obj-$(CONFIG_STM32_RESET) += stm32-reset.o
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obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
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obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
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obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
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obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
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obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
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obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
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obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
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obj-$(CONFIG_RESET_MESON) += reset-meson.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
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obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
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obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
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obj-$(CONFIG_RESET_QCOM) += reset-qcom.o
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obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
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obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
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obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
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obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
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obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
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obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
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obj-$(CONFIG_RESET_AT91) += reset-at91.o
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obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o
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