mirror of
https://github.com/AsahiLinux/u-boot
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862274913f
Move the bus initialization code to this driver from board files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#include <dm.h>
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/* System Bus Controller registers */
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#define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */
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#define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */
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#define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */
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#define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */
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#define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */
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#define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */
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#define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */
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#define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
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#if 1
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/* slower but LED works */
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#define SBCTRL0_VALUE 0x55450000
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#define SBCTRL1_VALUE 0x07168d00
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#define SBCTRL2_VALUE 0x34000009
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#define SBCTRL4_VALUE 0x02110110
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#else
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/* faster but LED does not work */
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#define SBCTRL0_VALUE 0x55450000
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#define SBCTRL1_VALUE 0x06057700
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/* NOR flash needs more wait counts than SRAM */
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#define SBCTRL2_VALUE 0x34000009
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#define SBCTRL4_VALUE 0x02110210
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#endif
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void uniphier_system_bus_set_reg(void __iomem *membase)
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{
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void __iomem *bank0_base = membase;
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void __iomem *bank1_base = membase + UNIPHIER_SBC_STRIDE;
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/*
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* Only CS1 is connected to support card.
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* BKSZ[1:0] should be set to "01".
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*/
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writel(SBCTRL0_VALUE, bank1_base + UNIPHIER_SBC_CTRL0);
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writel(SBCTRL1_VALUE, bank1_base + UNIPHIER_SBC_CTRL1);
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writel(SBCTRL2_VALUE, bank1_base + UNIPHIER_SBC_CTRL2);
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writel(SBCTRL4_VALUE, bank1_base + UNIPHIER_SBC_CTRL4);
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if (readl(bank1_base + UNIPHIER_SBC_BASE) & UNIPHIER_SBC_BASE_BE) {
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/*
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* Boot Swap On: boot from external NOR/SRAM
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* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
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*
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* 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
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* 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
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*/
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writel(0x0000bc01, bank0_base + UNIPHIER_SBC_BASE);
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} else {
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/*
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* Boot Swap Off: boot from mask ROM
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* 0x40000000-0x41ffffff: mask ROM
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* 0x42000000-0x43efffff: memory bank (31MB)
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* 0x43f00000-0x43ffffff: peripherals (1MB)
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*/
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writel(0x0000be01, bank0_base + UNIPHIER_SBC_BASE); /* dummy */
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writel(0x0200be01, bank0_base + UNIPHIER_SBC_BASE);
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}
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}
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static int uniphier_system_bus_probe(struct udevice *dev)
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{
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fdt_addr_t base;
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void __iomem *membase;
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base = dev_read_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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membase = devm_ioremap(dev, base, SZ_1K);
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if (!membase)
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return -ENOMEM;
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uniphier_system_bus_set_reg(membase);
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return 0;
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}
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static const struct udevice_id uniphier_system_bus_match[] = {
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{ .compatible = "socionext,uniphier-system-bus" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(uniphier_system_bus_driver) = {
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.name = "uniphier-system-bus",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = uniphier_system_bus_match,
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.probe = uniphier_system_bus_probe,
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};
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