u-boot/arch/riscv/cpu/ax25
Lukas Auer c9056653ec riscv: move the AX25-specific implementation of flush_dcache_all
The fence instruction is used to enforce device I/O and memory ordering
constraints in RISC-V. It can not be relied on to directly affect the
data cache on every CPU.
Andes' AX25 does not have a coherence agent. Its fence instruction
flushes the data cache and is used to keep data in the system coherent.
The implementation of flush_dcache_all in lib/cache.c is therefore
specific to the AX25. Move it into the AX25-specific cache.c in
cpu/ax25/.

This also adds a missing new line between flush_dcache_all and
flush_dcache_range in lib/cache.c.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15 09:36:31 +08:00
..
cache.c riscv: move the AX25-specific implementation of flush_dcache_all 2019-01-15 09:36:31 +08:00
cpu.c riscv: cache: Implement i/dcache [status, enable, disable] 2018-11-26 13:58:01 +08:00
Kconfig riscv: ax25: Hide the ax25-specific Kconfig option 2018-12-18 09:56:26 +08:00
Makefile riscv: cache: Implement i/dcache [status, enable, disable] 2018-11-26 13:58:01 +08:00