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Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode. If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode. If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
9 lines
295 B
Makefile
9 lines
295 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
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# Lokesh Vutla <lokeshvutla@ti.com>
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obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
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obj-$(CONFIG_ARM64) += arm64-mmu.o
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obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
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obj-y += common.o
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