mirror of
https://github.com/AsahiLinux/u-boot
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944b6ccf1b
1. fix 10G mac offset by plus 8; 2. add second 10G port info for FM1 & FM2 when init ethernet info; 3. fix 10G lanes name to match lane protocol table; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
134 lines
4.5 KiB
C
134 lines
4.5 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Roy Zang <tie-fei.zang@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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u32 port_to_devdisr[] = {
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[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
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[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
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[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
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[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
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[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
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[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
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[FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
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[FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
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[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
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[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
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[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
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[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
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[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
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[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
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[FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
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[FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
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[FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
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[FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
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[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
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[FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
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};
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static int is_device_disabled(enum fm_port port)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr2 = in_be32(&gur->devdisr2);
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return port_to_devdisr[port] & devdisr2;
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}
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void fman_disable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
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}
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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if (is_device_disabled(port))
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return PHY_INTERFACE_MODE_NONE;
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if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
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((is_serdes_configured(XAUI_FM1_MAC9)) ||
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(is_serdes_configured(XAUI_FM1_MAC10)) ||
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(is_serdes_configured(XFI_FM1_MAC9)) ||
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(is_serdes_configured(XFI_FM1_MAC10))))
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return PHY_INTERFACE_MODE_XGMII;
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if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
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((is_serdes_configured(XAUI_FM2_MAC9)) ||
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(is_serdes_configured(XAUI_FM2_MAC10)) ||
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(is_serdes_configured(XFI_FM2_MAC9)) ||
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(is_serdes_configured(XFI_FM2_MAC10))))
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return PHY_INTERFACE_MODE_XGMII;
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#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
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#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
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#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
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#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
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#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
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#define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000
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#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
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/* handle RGMII first */
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if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
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FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
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FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
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FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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case FM1_DTSEC3:
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case FM1_DTSEC4:
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case FM1_DTSEC5:
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case FM1_DTSEC6:
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case FM1_DTSEC9:
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case FM1_DTSEC10:
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if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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break;
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case FM2_DTSEC1:
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case FM2_DTSEC2:
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case FM2_DTSEC3:
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case FM2_DTSEC4:
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case FM2_DTSEC5:
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case FM2_DTSEC6:
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case FM2_DTSEC9:
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case FM2_DTSEC10:
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if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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break;
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default:
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return PHY_INTERFACE_MODE_NONE;
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}
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return PHY_INTERFACE_MODE_NONE;
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}
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