mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
5713135ecc
Enable CONFIG_ROCKCHIP_SPI_IMAGE to build u-boot-rockchip-spi.bin. Define CONFIG_SYS_SPI_U_BOOT_OFFS to write u-boot.itb at the expected offset. Enable CONFIG_LTO to reduce size of SPL so that the mkimage output fit before the 0x60000 offset in u-boot-rockchip-spi.bin. => sf probe SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1442304 bytes read in 27 ms (50.9 MiB/s) => sf update $fileaddr 0 $filesize device 0 offset 0x0, size 0x160200 1421824 bytes written, 20480 bytes skipped in 9.501s, speed 155432 B/s Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
114 lines
2.9 KiB
Text
114 lines
2.9 KiB
Text
CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_TEXT_BASE=0x00200000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
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CONFIG_ENV_SIZE=0x8000
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
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CONFIG_DM_RESET=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_SPI_IMAGE=y
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CONFIG_TARGET_ROCKPRO64_RK3399=y
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CONFIG_SPL_STACK=0x400000
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_SYS_LOAD_ADDR=0x800800
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CONFIG_PCI=y
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CONFIG_DEBUG_UART=y
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CONFIG_LTO=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_BOOTSTAGE=y
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CONFIG_BOOTSTAGE_REPORT=y
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CONFIG_USE_PREBOOT=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_MISC_INIT_R=y
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CONFIG_SPL_MAX_SIZE=0x2e000
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CONFIG_SPL_PAD_TO=0x7f8000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x400000
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CONFIG_SPL_BSS_MAX_SIZE=0x2000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
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CONFIG_TPL=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TIME=y
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CONFIG_CMD_BOOTSTAGE=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SATA=y
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CONFIG_SCSI_AHCI=y
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CONFIG_AHCI_PCI=y
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CONFIG_SATA_SIL=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_MISC=y
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CONFIG_ROCKCHIP_EFUSE=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_NVME_PCI=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_TYPEC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RAM_ROCKCHIP_LPDDR4=y
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CONFIG_DM_RNG=y
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CONFIG_RNG_ROCKCHIP=y
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CONFIG_SCSI=y
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CONFIG_DM_SCSI=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_ROCKCHIP_SPI=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_GENERIC=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_USB_KEYBOARD=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_ASIX88179=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_RTL8152=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_VIDEO=y
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CONFIG_DISPLAY=y
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CONFIG_VIDEO_ROCKCHIP=y
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CONFIG_DISPLAY_ROCKCHIP_HDMI=y
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_ERRNO_STR=y
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