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948d811882
T4240 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
150 lines
3.8 KiB
Text
150 lines
3.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* T4240 Silicon/SoC Device Tree Source (pre include)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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/include/ "e6500_power_isa.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,e6500@0 {
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device_type = "cpu";
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reg = <0 1>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu1: PowerPC,e6500@2 {
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device_type = "cpu";
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reg = <2 3>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu2: PowerPC,e6500@4 {
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device_type = "cpu";
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reg = <4 5>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu3: PowerPC,e6500@6 {
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device_type = "cpu";
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reg = <6 7>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu4: PowerPC,e6500@8 {
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device_type = "cpu";
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reg = <8 9>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu5: PowerPC,e6500@10 {
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device_type = "cpu";
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reg = <10 11>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu6: PowerPC,e6500@12 {
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device_type = "cpu";
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reg = <12 13>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu7: PowerPC,e6500@14 {
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device_type = "cpu";
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reg = <14 15>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu8: PowerPC,e6500@16 {
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device_type = "cpu";
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reg = <16 17>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu9: PowerPC,e6500@18 {
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device_type = "cpu";
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reg = <18 19>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu10: PowerPC,e6500@20 {
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device_type = "cpu";
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reg = <20 21>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu11: PowerPC,e6500@22 {
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device_type = "cpu";
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reg = <22 23>;
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fsl,portid-mapping = <0x80000000>;
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};
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <4>;
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reg = <0x40000 0x40000>;
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compatible = "fsl,mpic";
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device_type = "open-pic";
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clock-frequency = <0x0>;
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};
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};
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pcie@ffe240000 {
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compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
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reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */
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law_trgt_if = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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pcie@ffe250000 {
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compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
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reg = <0xf 0xfe250000 0x0 0x4000>; /* registers */
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law_trgt_if = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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pcie@ffe260000 {
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compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
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reg = <0xf 0xfe260000 0x0 0x4000>; /* registers */
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law_trgt_if = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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pcie@ffe270000 {
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compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
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reg = <0xf 0xfe270000 0x0 0x4000>; /* registers */
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law_trgt_if = <3>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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};
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