mirror of
https://github.com/AsahiLinux/u-boot
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f6bbec3d5c
Unfortunately, this SoC needs per-board adjustment between clock and address/command lines. This flag will be passed to the DRAM init function and used for compensating the difference of DRAM timing parameters. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
296 lines
5.9 KiB
C
296 lines
5.9 KiB
C
/*
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <linux/kernel.h>
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#include "init.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
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static const struct uniphier_board_data uniphier_sld3_data = {
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.dram_freq = 1600,
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.dram_nr_ch = 3,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x20000000,
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.width = 32,
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},
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.dram_ch[1] = {
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.base = 0xc0000000,
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.size = 0x20000000,
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.width = 16,
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},
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.dram_ch[2] = {
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.base = 0xc0000000,
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.size = 0x10000000,
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.width = 16,
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},
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_LD4)
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static const struct uniphier_board_data uniphier_ld4_data = {
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.dram_freq = 1600,
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.dram_nr_ch = 2,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x10000000,
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.width = 16,
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},
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.dram_ch[1] = {
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.base = 0x90000000,
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.size = 0x10000000,
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.width = 16,
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},
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.flags = UNIPHIER_BD_DDR3PLUS,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
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/* 1GB RAM board */
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static const struct uniphier_board_data uniphier_pro4_data = {
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.dram_freq = 1600,
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.dram_nr_ch = 2,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x20000000,
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.width = 32,
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},
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.dram_ch[1] = {
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.base = 0xa0000000,
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.size = 0x20000000,
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.width = 32,
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},
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};
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/* 2GB RAM board */
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static const struct uniphier_board_data uniphier_pro4_2g_data = {
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.dram_freq = 1600,
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.dram_nr_ch = 2,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x40000000,
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.width = 32,
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},
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.dram_ch[1] = {
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.base = 0xc0000000,
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.size = 0x40000000,
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.width = 32,
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},
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
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static const struct uniphier_board_data uniphier_sld8_data = {
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.dram_freq = 1333,
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.dram_nr_ch = 2,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x10000000,
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.width = 16,
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},
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.dram_ch[1] = {
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.base = 0x90000000,
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.size = 0x10000000,
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.width = 16,
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},
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.flags = UNIPHIER_BD_DDR3PLUS,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
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static const struct uniphier_board_data uniphier_pro5_data = {
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.dram_freq = 1866,
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.dram_nr_ch = 2,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x20000000,
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.width = 32,
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},
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.dram_ch[1] = {
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.base = 0xa0000000,
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.size = 0x20000000,
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.width = 32,
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},
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
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static const struct uniphier_board_data uniphier_pxs2_data = {
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.dram_freq = 2133,
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.dram_nr_ch = 3,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x40000000,
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.width = 32,
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},
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.dram_ch[1] = {
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.base = 0xc0000000,
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.size = 0x20000000,
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.width = 32,
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},
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.dram_ch[2] = {
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.base = 0xe0000000,
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.size = 0x20000000,
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.width = 16,
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},
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
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static const struct uniphier_board_data uniphier_ld6b_data = {
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.dram_freq = 1866,
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.dram_nr_ch = 3,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x40000000,
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.width = 32,
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},
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.dram_ch[1] = {
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.base = 0xc0000000,
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.size = 0x20000000,
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.width = 32,
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},
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.dram_ch[2] = {
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.base = 0xe0000000,
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.size = 0x20000000,
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.width = 16,
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},
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_LD11)
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static const struct uniphier_board_data uniphier_ld11_data = {
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.dram_freq = 1600,
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.dram_nr_ch = 2,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x20000000,
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.width = 16,
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},
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.dram_ch[1] = {
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.base = 0xa0000000,
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.size = 0x20000000,
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.width = 16,
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},
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_LD20)
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static const struct uniphier_board_data uniphier_ld20_ref_data = {
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.dram_freq = 1866,
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.dram_nr_ch = 3,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x40000000,
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.width = 32,
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},
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.dram_ch[1] = {
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.base = 0xc0000000,
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.size = 0x40000000,
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.width = 32,
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},
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.dram_ch[2] = {
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.base = 0x100000000UL,
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.size = 0x40000000,
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.width = 32,
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},
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.flags = UNIPHIER_BD_BOARD_LD20_REF,
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};
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static const struct uniphier_board_data uniphier_ld20_data = {
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.dram_freq = 1866,
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.dram_nr_ch = 3,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x40000000,
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.width = 32,
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},
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.dram_ch[1] = {
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.base = 0xc0000000,
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.size = 0x40000000,
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.width = 32,
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},
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.dram_ch[2] = {
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.base = 0x100000000UL,
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.size = 0x40000000,
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.width = 32,
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},
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.flags = UNIPHIER_BD_BOARD_LD20_GLOBAL,
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};
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static const struct uniphier_board_data uniphier_ld21_data = {
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.dram_freq = 1866,
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.dram_nr_ch = 2,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x20000000,
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.width = 32,
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},
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.dram_ch[1] = {
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.base = 0xc0000000,
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.size = 0x40000000,
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.width = 32,
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},
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.flags = UNIPHIER_BD_BOARD_LD21_GLOBAL,
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};
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#endif
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struct uniphier_board_id {
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const char *compatible;
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const struct uniphier_board_data *param;
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};
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static const struct uniphier_board_id uniphier_boards[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
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{ "socionext,ph1-sld3", &uniphier_sld3_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_LD4)
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{ "socionext,ph1-ld4", &uniphier_ld4_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
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{ "socionext,ph1-pro4-ace", &uniphier_pro4_2g_data, },
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{ "socionext,ph1-pro4-sanji", &uniphier_pro4_2g_data, },
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{ "socionext,ph1-pro4", &uniphier_pro4_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
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{ "socionext,ph1-sld8", &uniphier_sld8_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
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{ "socionext,ph1-pro5", &uniphier_pro5_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
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{ "socionext,proxstream2", &uniphier_pxs2_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
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{ "socionext,ph1-ld6b", &uniphier_ld6b_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_LD11)
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{ "socionext,ph1-ld11", &uniphier_ld11_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_LD20)
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{ "socionext,ph1-ld21", &uniphier_ld21_data, },
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{ "socionext,ph1-ld20-ref", &uniphier_ld20_ref_data, },
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{ "socionext,ph1-ld20", &uniphier_ld20_data, },
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#endif
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};
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const struct uniphier_board_data *uniphier_get_board_param(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
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if (!fdt_node_check_compatible(gd->fdt_blob, 0,
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uniphier_boards[i].compatible))
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return uniphier_boards[i].param;
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}
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return NULL;
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}
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