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AT91 PIO controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. Each SoC will have to describe the its limitation and pin configuration via device tree. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
42 lines
1.2 KiB
C
42 lines
1.2 KiB
C
/*
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* This header provides constants for most at91 pinctrl bindings.
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*
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* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* GPLv2 only
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*/
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#ifndef __DT_BINDINGS_AT91_PINCTRL_H__
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#define __DT_BINDINGS_AT91_PINCTRL_H__
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#define AT91_PINCTRL_NONE (0 << 0)
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#define AT91_PINCTRL_PULL_UP (1 << 0)
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#define AT91_PINCTRL_MULTI_DRIVE (1 << 1)
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#define AT91_PINCTRL_DEGLITCH (1 << 2)
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#define AT91_PINCTRL_PULL_DOWN (1 << 3)
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#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
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#define AT91_PINCTRL_OUTPUT (1 << 7)
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#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
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#define AT91_PINCTRL_DEBOUNCE (1 << 16)
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#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
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#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
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#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5)
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#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
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#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
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#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
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#define AT91_PIOA 0
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#define AT91_PIOB 1
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#define AT91_PIOC 2
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#define AT91_PIOD 3
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#define AT91_PIOE 4
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#define AT91_PERIPH_GPIO 0
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#define AT91_PERIPH_A 1
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#define AT91_PERIPH_B 2
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#define AT91_PERIPH_C 3
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#define AT91_PERIPH_D 4
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#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */
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