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148 lines
6.9 KiB
C
148 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* This header file contains assembly-language definitions (assembly
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* macros, etc.) for this specific Xtensa processor's TIE extensions
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* and options. It is customized to this Xtensa processor configuration.
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* This file is autogenerated, please do not edit.
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*
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* Copyright (C) 1999-2015 Cadence Design Systems Inc.
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*/
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#ifndef _XTENSA_CORE_TIE_ASM_H
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#define _XTENSA_CORE_TIE_ASM_H
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/* Selection parameter values for save-area save/restore macros: */
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/* Option vs. TIE: */
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#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
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#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
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#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
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/* Whether used automatically by compiler: */
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#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
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#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
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#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
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/* ABI handling across function calls: */
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#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
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#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
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#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
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#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
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/* Misc */
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
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#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
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| ((ccuse) & XTHAL_SAS_ANYCC) \
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| ((abi) & XTHAL_SAS_ANYABI) )
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/*
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* Macro to store all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 4 byte aligned address).
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* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
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* registers are clobbered, the remaining are unused).
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* Optional parameters:
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* continue If macro invoked as part of a larger store sequence, set to 1
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* if this is not the first in the sequence. Defaults to 0.
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* ofs Offset from start of larger sequence (from value of first ptr
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* in sequence) at which to store. Defaults to next available space
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* (or 0 if <continue> is 0).
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* select Select what category(ies) of registers to store, as a bitmask
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* (see XTHAL_SAS_xxx constants). Defaults to all registers.
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* alloc Select what category(ies) of registers to allocate; if any
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* category is selected here that is not in <select>, space for
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* the corresponding registers is skipped without doing any store.
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*/
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.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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// Optional caller-saved registers used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1016, 4, 4
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rsr.ACCLO \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+0
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rsr.ACCHI \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1016, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.endif
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// Optional caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1004, 4, 4
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rsr.SCOMPARE1 \at1 // conditional store option
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s32i \at1, \ptr, .Lxchal_ofs_+0
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rsr.M0 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+4
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rsr.M1 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+8
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rsr.M2 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+12
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rsr.M3 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+16
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 20
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1004, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 20
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.endif
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.endm // xchal_ncp_store
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/*
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* Macro to load all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 4 byte aligned address).
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* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
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* registers are clobbered, the remaining are unused).
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* Optional parameters:
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* continue If macro invoked as part of a larger load sequence, set to 1
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* if this is not the first in the sequence. Defaults to 0.
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* ofs Offset from start of larger sequence (from value of first ptr
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* in sequence) at which to load. Defaults to next available space
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* (or 0 if <continue> is 0).
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* select Select what category(ies) of registers to load, as a bitmask
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* (see XTHAL_SAS_xxx constants). Defaults to all registers.
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* alloc Select what category(ies) of registers to allocate; if any
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* category is selected here that is not in <select>, space for
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* the corresponding registers is skipped without doing any load.
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*/
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.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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// Optional caller-saved registers used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1016, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wsr.ACCLO \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+4
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wsr.ACCHI \at1 // MAC16 option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1016, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.endif
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// Optional caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1004, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wsr.SCOMPARE1 \at1 // conditional store option
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l32i \at1, \ptr, .Lxchal_ofs_+4
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wsr.M0 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+8
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wsr.M1 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+12
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wsr.M2 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+16
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wsr.M3 \at1 // MAC16 option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 20
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1004, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 20
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.endif
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.endm // xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS 1
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#define XCHAL_SA_NUM_ATMPS 1
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#endif /*_XTENSA_CORE_TIE_ASM_H*/
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