mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 18:53:06 +00:00
7e270ec3af
The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor. - Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705 These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.). Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
137 lines
2.8 KiB
Text
137 lines
2.8 KiB
Text
/ {
|
|
compatible = "cdns,xtensa-xtfpga";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-parent = <&pic>;
|
|
|
|
chosen {
|
|
bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x06000000>;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cpu@0 {
|
|
compatible = "cdns,xtensa-cpu";
|
|
reg = <0>;
|
|
/* Filled in by platform_setup from FPGA register
|
|
* clock-frequency = <100000000>;
|
|
*/
|
|
};
|
|
};
|
|
|
|
pic: pic {
|
|
compatible = "cdns,xtensa-pic";
|
|
/* one cell: internal irq number,
|
|
* two cells: second cell == 0: internal irq number
|
|
* second cell == 1: external irq number
|
|
*/
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
clocks {
|
|
osc: main-oscillator {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
};
|
|
|
|
clk54: clk54 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <54000000>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
ranges = <0x00000000 0xf0000000 0x10000000>;
|
|
|
|
serial0: serial@0d050020 {
|
|
device_type = "serial";
|
|
compatible = "ns16550a";
|
|
no-loopback-test;
|
|
reg = <0x0d050020 0x20>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
native-endian;
|
|
interrupts = <0 1>; /* external irq 0 */
|
|
clocks = <&osc>;
|
|
};
|
|
|
|
enet0: ethoc@0d030000 {
|
|
compatible = "opencores,ethoc";
|
|
reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
|
|
native-endian;
|
|
interrupts = <1 1>; /* external irq 1 */
|
|
local-mac-address = [00 50 c2 13 6f 00];
|
|
clocks = <&osc>;
|
|
};
|
|
|
|
i2s0: xtfpga-i2s@0d080000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "cdns,xtfpga-i2s";
|
|
reg = <0x0d080000 0x40>;
|
|
interrupts = <2 1>; /* external irq 2 */
|
|
clocks = <&cdce706 4>;
|
|
};
|
|
|
|
i2c0: i2c-master@0d090000 {
|
|
compatible = "opencores,i2c-ocores";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0d090000 0x20>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
native-endian;
|
|
interrupts = <4 1>;
|
|
clocks = <&osc>;
|
|
|
|
cdce706: clock-synth@69 {
|
|
compatible = "ti,cdce706";
|
|
#clock-cells = <1>;
|
|
reg = <0x69>;
|
|
clocks = <&clk54>;
|
|
clock-names = "clk_in0";
|
|
};
|
|
};
|
|
|
|
spi0: spi-master@0d0a0000 {
|
|
compatible = "cdns,xtfpga-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0d0a0000 0xc>;
|
|
|
|
tlv320aic23: sound-codec@0 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "tlv320aic23";
|
|
reg = <0>;
|
|
spi-max-frequency = <12500000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sound {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,format = "i2s";
|
|
simple-audio-card,mclk-fs = <256>;
|
|
|
|
simple-audio-card,cpu {
|
|
sound-dai = <&i2s0>;
|
|
};
|
|
|
|
simple-audio-card,codec {
|
|
sound-dai = <&tlv320aic23>;
|
|
simple-audio-card,bitclock-master = <0>;
|
|
simple-audio-card,frame-master = <0>;
|
|
clocks = <&cdce706 4>;
|
|
};
|
|
};
|
|
};
|