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f6aebdf676
Versal NET platform is based on Versal chip which is reusing a lot of IPs. For more information about new IPs please take a look at DT which describe currently supported devices. The patch is adding architecture and board support with soc detection algorithm. Generic setting should be very similar to Versal but it will likely diverge in longer run. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com
35 lines
719 B
C
35 lines
719 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 - 2022, Xilinx, Inc.
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* Copyright (C) 2022, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <time.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CLOCKS
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/**
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* set_cpu_clk_info - Initialize clock framework
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*
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* Return: 0 always.
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*
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* This function is called from common code after relocation and sets up the
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* clock framework. The framework must not be used before this function had been
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* called.
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*/
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int set_cpu_clk_info(void)
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{
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gd->cpu_clk = get_tbclk();
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gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
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gd->bd->bi_dsp_freq = 0;
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return 0;
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}
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#endif
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