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5a3b074255
This adds R-Car Generation 4 (Gen4) support as Renesas ARM64 SoC.
In this version, reusing R-Car Gen3 lowlevel initialize routine [1]
and R-Car Gen3 memory map tables [2] .
[1] arch/arm/mach-rmobile/lowlevel_init_gen3.S
[2] arch/arm/mach-rmobile/memmap-gen3.c
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: - Enable DTO support by default
- Sort the Kconfig lists
- Select RCAR_64 Kconfig option to pull in all the shared
Kconfig options with Gen3, and use where applicable to
deduplicate entries.
- Fix reference [2] typo in commit message
- Drop config options moved to Kconfig, rename rest to CFG_
accordingly to synchronize with upstream changes. Drop
removed CONFIG_VERY_BIG_RAM.
- Move board size limit to arch/Kconfig
- Move GICR_BASE to headers instead of common config]
75 lines
1.6 KiB
C
75 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* ./arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#ifndef __ASM_ARCH_RCAR_GEN4_BASE_H
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#define __ASM_ARCH_RCAR_GEN4_BASE_H
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/*
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* R-Car (R8A779F0) I/O Addresses
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*/
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#define RWDT_BASE 0xE6020000
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#define SWDT_BASE 0xE6030000
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#define TMU_BASE 0xE61E0000
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/* SCIF */
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#define SCIF0_BASE 0xE6E60000
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#define SCIF1_BASE 0xE6E68000
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#define SCIF2_BASE 0xE6E88000
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#define SCIF3_BASE 0xE6C50000
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#define SCIF4_BASE 0xE6C40000
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#define SCIF5_BASE 0xE6F30000
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/* CPG */
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#define CPGWPR 0xE6150000
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#define CPGWPCR 0xE6150004
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/* Reset */
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#define RST_BASE 0xE6160000 /* Domain0 */
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#define RST_SRESCR0 (RST_BASE + 0x18)
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#define RST_SPRES 0x5AA58000
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/* Arm Generic Timer */
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#define CNTCR_BASE 0xE6080000
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#define CNTFID0 (CNTCR_BASE + 0x020)
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#define CNTCR_EN BIT(0)
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/* GICv3 */
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/* Distributor Registers */
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#define GICD_BASE 0xF1000000
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#define GICR_BASE (GICR_LPI_BASE)
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/* ReDistributor Registers for Control and Physical LPIs */
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#define GICR_LPI_BASE 0xF1060000
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#define GICR_WAKER 0x0014
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#define GICR_PWRR 0x0024
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#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
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#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR)
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/* ReDistributor Registers for SGIs and PPIs */
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#define GICR_SGI_BASE 0xF1070000
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#define GICR_IGROUPR0 0x0080
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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#include <linux/bitops.h>
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/* RWDT */
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struct rcar_rwdt {
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u32 rwtcnt;
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u32 rwtcsra;
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u32 rwtcsrb;
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};
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/* SWDT */
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struct rcar_swdt {
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u32 swtcnt;
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u32 swtcsra;
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u32 swtcsrb;
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};
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#endif
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#endif /* __ASM_ARCH_RCAR_GEN4_BASE_H */
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