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9dbe356ef4
Perform a simple rename of CONFIG_SAR_REG to CFG_SAR_REG Signed-off-by: Tom Rini <trini@konsulko.com>
21 lines
582 B
C
21 lines
582 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC.
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*/
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#ifndef _ASM_ARCH_KW88F6281_H
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#define _ASM_ARCH_KW88F6281_H
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/* SOC specific definitions */
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#define KW88F6281_REGS_PHYS_BASE 0xf1000000
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#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
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/* TCLK Core Clock definition */
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#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(21)) ? \
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166666667 : 200000000)
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#endif /* _ASM_ARCH_KW88F6281_H */
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