mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 02:33:07 +00:00
b511b371ad
Introduce the mach-k3 files needed to properly boot TI's am62a SoC family of devices Signed-off-by: Bryan Brattlof <bb@ti.com>
266 lines
6.3 KiB
C
266 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* K3: ARM64 MMU setup
|
|
*
|
|
* Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
|
|
* Lokesh Vutla <lokeshvutla@ti.com>
|
|
* Suman Anna <s-anna@ti.com>
|
|
* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
|
|
*
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/system.h>
|
|
#include <asm/armv8/mmu.h>
|
|
|
|
#ifdef CONFIG_SOC_K3_AM654
|
|
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
|
|
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
|
|
|
|
/* ToDo: Add 64bit IO */
|
|
struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
|
|
{
|
|
.virt = 0x0UL,
|
|
.phys = 0x0UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x80000000UL,
|
|
.phys = 0x80000000UL,
|
|
.size = 0x20000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0xa0000000UL,
|
|
.phys = 0xa0000000UL,
|
|
.size = 0x02100000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0xa2100000UL,
|
|
.phys = 0xa2100000UL,
|
|
.size = 0x5df00000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x880000000UL,
|
|
.phys = 0x880000000UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x500000000UL,
|
|
.phys = 0x500000000UL,
|
|
.size = 0x400000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
/* List terminator */
|
|
0,
|
|
}
|
|
};
|
|
|
|
struct mm_region *mem_map = am654_mem_map;
|
|
#endif /* CONFIG_SOC_K3_AM654 */
|
|
|
|
#ifdef CONFIG_SOC_K3_J721E
|
|
|
|
#ifdef CONFIG_TARGET_J721E_A72_EVM
|
|
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
|
|
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
|
|
|
|
/* ToDo: Add 64bit IO */
|
|
struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
|
|
{
|
|
.virt = 0x0UL,
|
|
.phys = 0x0UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x80000000UL,
|
|
.phys = 0x80000000UL,
|
|
.size = 0x20000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0xa0000000UL,
|
|
.phys = 0xa0000000UL,
|
|
.size = 0x1bc00000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
|
|
PTE_BLOCK_NON_SHARE
|
|
}, {
|
|
.virt = 0xbbc00000UL,
|
|
.phys = 0xbbc00000UL,
|
|
.size = 0x44400000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x880000000UL,
|
|
.phys = 0x880000000UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x500000000UL,
|
|
.phys = 0x500000000UL,
|
|
.size = 0x400000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x4d80000000UL,
|
|
.phys = 0x4d80000000UL,
|
|
.size = 0x0002000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
/* List terminator */
|
|
0,
|
|
}
|
|
};
|
|
|
|
struct mm_region *mem_map = j721e_mem_map;
|
|
#endif /* CONFIG_TARGET_J721E_A72_EVM */
|
|
|
|
#ifdef CONFIG_TARGET_J7200_A72_EVM
|
|
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
|
|
|
|
/* ToDo: Add 64bit IO */
|
|
struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
|
|
{
|
|
.virt = 0x0UL,
|
|
.phys = 0x0UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x80000000UL,
|
|
.phys = 0x80000000UL,
|
|
.size = 0x20000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0xa0000000UL,
|
|
.phys = 0xa0000000UL,
|
|
.size = 0x04800000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
|
|
PTE_BLOCK_NON_SHARE
|
|
}, {
|
|
.virt = 0xa4800000UL,
|
|
.phys = 0xa4800000UL,
|
|
.size = 0x5b800000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x880000000UL,
|
|
.phys = 0x880000000UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x500000000UL,
|
|
.phys = 0x500000000UL,
|
|
.size = 0x400000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
/* List terminator */
|
|
0,
|
|
}
|
|
};
|
|
|
|
struct mm_region *mem_map = j7200_mem_map;
|
|
#endif /* CONFIG_TARGET_J7200_A72_EVM */
|
|
|
|
#endif /* CONFIG_SOC_K3_J721E */
|
|
|
|
#ifdef CONFIG_SOC_K3_J721S2
|
|
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
|
|
|
|
/* ToDo: Add 64bit IO */
|
|
struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
|
|
{
|
|
.virt = 0x0UL,
|
|
.phys = 0x0UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x80000000UL,
|
|
.phys = 0x80000000UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x880000000UL,
|
|
.phys = 0x880000000UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x500000000UL,
|
|
.phys = 0x500000000UL,
|
|
.size = 0x400000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
/* List terminator */
|
|
0,
|
|
}
|
|
};
|
|
|
|
struct mm_region *mem_map = j721s2_mem_map;
|
|
|
|
#endif /* CONFIG_SOC_K3_J721S2 */
|
|
|
|
#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \
|
|
defined(CONFIG_SOC_K3_AM62A7)
|
|
|
|
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
|
|
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
|
|
|
|
/* ToDo: Add 64bit IO */
|
|
struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
|
|
{
|
|
.virt = 0x0UL,
|
|
.phys = 0x0UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x80000000UL,
|
|
.phys = 0x80000000UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x880000000UL,
|
|
.phys = 0x880000000UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0x500000000UL,
|
|
.phys = 0x500000000UL,
|
|
.size = 0x400000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
/* List terminator */
|
|
0,
|
|
}
|
|
};
|
|
|
|
struct mm_region *mem_map = am64_mem_map;
|
|
#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
|