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8a897c4f97
Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
111 lines
2.4 KiB
C
111 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Miscelaneous DaVinci functions.
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*
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* Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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* Copyright (C) 2004 Texas Instruments.
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*/
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#include <common.h>
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#include <env.h>
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#include <i2c.h>
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#include <init.h>
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#include <log.h>
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#include <net.h>
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#include <asm/arch/hardware.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/davinci_misc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SPL_BUILD
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size(
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(void *)CFG_SYS_SDRAM_BASE,
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CFG_MAX_RAM_BANK_SIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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#endif
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#ifdef CONFIG_DRIVER_TI_EMAC
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/*
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* Set the mii mode as MII or RMII
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*/
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void davinci_emac_mii_mode_sel(int mode_sel)
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{
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int val;
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val = readl(&davinci_syscfg_regs->cfgchip3);
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if (mode_sel == 0)
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val &= ~(1 << 8);
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else
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val |= (1 << 8);
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writel(val, &davinci_syscfg_regs->cfgchip3);
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}
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/*
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* If there is no MAC address in the environment, then it will be initialized
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* (silently) from the value in the EEPROM.
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*/
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void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
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{
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uint8_t env_enetaddr[6];
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int ret;
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ret = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
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if (!ret) {
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/*
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* There is no MAC address in the environment, so we
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* initialize it from the value in the EEPROM.
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*/
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debug("### Setting environment from EEPROM MAC address = "
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"\"%pM\"\n",
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env_enetaddr);
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ret = !eth_env_set_enetaddr("ethaddr", rom_enetaddr);
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}
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if (!ret)
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printf("Failed to set mac address from EEPROM: %d\n", ret);
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}
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#endif /* CONFIG_DRIVER_TI_EMAC */
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void irq_init(void)
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{
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/*
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* Mask all IRQs by clearing the global enable and setting
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* the enable clear for all the 90 interrupts.
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*/
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writel(0, &davinci_aintc_regs->ger);
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writel(0, &davinci_aintc_regs->hier);
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writel(0xffffffff, &davinci_aintc_regs->ecr1);
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writel(0xffffffff, &davinci_aintc_regs->ecr2);
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writel(0xffffffff, &davinci_aintc_regs->ecr3);
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}
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/*
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* Enable PSC for various peripherals.
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*/
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int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
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const int n_items)
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{
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int i;
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for (i = 0; i < n_items; i++)
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lpsc_on(item[i].lpsc_no);
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return 0;
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}
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