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https://github.com/AsahiLinux/u-boot
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887e2ec9ec
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
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/*----------------------------------------------------------------------------+
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| File Name: mal.h
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| Function: Header file for the MAL (MADMAL) macro on the 405GP.
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 29-Apr-99 Created MKW
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
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| Added register bit definitions to support multiple channels
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+----------------------------------------------------------------------------*/
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#ifndef _mal_h_
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#define _mal_h_
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/* MADMAL transmit and receive status/control bits */
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/* for COMMAC bits, refer to the COMMAC header file */
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#define MAL_TX_CTRL_READY 0x8000
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#define MAL_TX_CTRL_WRAP 0x4000
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#define MAL_TX_CTRL_CM 0x2000
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#define MAL_TX_CTRL_LAST 0x1000
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#define MAL_TX_CTRL_INTR 0x0400
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#define MAL_RX_CTRL_EMPTY 0x8000
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#define MAL_RX_CTRL_WRAP 0x4000
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#define MAL_RX_CTRL_CM 0x2000
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#define MAL_RX_CTRL_LAST 0x1000
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#define MAL_RX_CTRL_FIRST 0x0800
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#define MAL_RX_CTRL_INTR 0x0400
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/* Configuration Reg */
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#define MAL_CR_MMSR 0x80000000
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#define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */
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#define MAL_CR_PLBP_2 0x00800000
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#define MAL_CR_PLBP_3 0x00C00000 /* highest */
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#define MAL_CR_GA 0x00200000
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#define MAL_CR_OA 0x00100000
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#define MAL_CR_PLBLE 0x00080000
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#define MAL_CR_PLBLT_1 0x00040000
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#define MAL_CR_PLBLT_2 0x00020000
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#define MAL_CR_PLBLT_3 0x00010000
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#define MAL_CR_PLBLT_4 0x00008000
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#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
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#define MAL_CR_PLBB 0x00004000
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#define MAL_CR_OPBBL 0x00000080
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#define MAL_CR_EOPIE 0x00000004
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#define MAL_CR_LEA 0x00000002
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#define MAL_CR_MSD 0x00000001
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/* Error Status Reg */
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#define MAL_ESR_EVB 0x80000000
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#define MAL_ESR_CID 0x40000000
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#define MAL_ESR_DE 0x00100000
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#define MAL_ESR_ONE 0x00080000
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#define MAL_ESR_OTE 0x00040000
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#define MAL_ESR_OSE 0x00020000
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#define MAL_ESR_PEIN 0x00010000
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/* same bit position as the IER */
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/* VV VV */
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#define MAL_ESR_DEI 0x00000010
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#define MAL_ESR_ONEI 0x00000008
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#define MAL_ESR_OTEI 0x00000004
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#define MAL_ESR_OSEI 0x00000002
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#define MAL_ESR_PBEI 0x00000001
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/* ^^ ^^ */
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/* Mal IER */
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define MAL_IER_PT 0x00000080
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#define MAL_IER_PRE 0x00000040
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#define MAL_IER_PWE 0x00000020
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#define MAL_IER_DE 0x00000010
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#define MAL_IER_OTE 0x00000004
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#define MAL_IER_OE 0x00000002
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#define MAL_IER_PE 0x00000001
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#else
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#define MAL_IER_DE 0x00000010
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#define MAL_IER_NE 0x00000008
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#define MAL_IER_TE 0x00000004
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#define MAL_IER_OPBE 0x00000002
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#define MAL_IER_PLBE 0x00000001
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#endif
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/* MAL Channel Active Set and Reset Registers */
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#define MAL_TXRX_CASR (0x80000000)
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#define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */
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/* MAL Buffer Descriptor structure */
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typedef struct {
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short ctrl; /* MAL / Commac status control bits */
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short data_len; /* Max length is 4K-1 (12 bits) */
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char *data_ptr; /* pointer to actual data buffer */
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} mal_desc_t;
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#endif
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