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93f93fe4cd
Now that all differences in functionality are covered by individual flags, remove the enumeration of SoC variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
936 lines
24 KiB
C
936 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016
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* Author: Amit Singh Tomar, amittomer25@gmail.com
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*
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* Ethernet driver for H3/A64/A83T based SoC's
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*
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* It is derived from the work done by
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* LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
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*
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*/
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#include <cpu_func.h>
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#include <log.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdt_support.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#include <reset.h>
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#include <wait_bit.h>
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#define MDIO_CMD_MII_BUSY BIT(0)
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#define MDIO_CMD_MII_WRITE BIT(1)
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#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
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#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
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#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
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#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
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#define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0
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#define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1
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#define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2
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#define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
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#define MDIO_CMD_MII_CLK_CSR_SHIFT 20
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#define CFG_TX_DESCR_NUM 32
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#define CFG_RX_DESCR_NUM 32
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#define CFG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
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/*
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* The datasheet says that each descriptor can transfers up to 4096 bytes
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* But later, the register documentation reduces that value to 2048,
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* using 2048 cause strange behaviours and even BSP driver use 2047
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*/
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#define CFG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
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#define TX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
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#define RX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
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#define H3_EPHY_DEFAULT_VALUE 0x58000
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#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
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#define H3_EPHY_ADDR_SHIFT 20
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#define REG_PHY_ADDR_MASK GENMASK(4, 0)
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#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
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#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
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#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
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#define SC_RMII_EN BIT(13)
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#define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
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#define SC_ETCS_MASK GENMASK(1, 0)
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#define SC_ETCS_EXT_GMII 0x1
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#define SC_ETCS_INT_GMII 0x2
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#define SC_ETXDC_MASK GENMASK(12, 10)
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#define SC_ETXDC_OFFSET 10
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#define SC_ERXDC_MASK GENMASK(9, 5)
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#define SC_ERXDC_OFFSET 5
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#define CFG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define AHB_GATE_OFFSET_EPHY 0
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/* H3/A64 EMAC Register's offset */
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#define EMAC_CTL0 0x00
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#define EMAC_CTL0_FULL_DUPLEX BIT(0)
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#define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
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#define EMAC_CTL0_SPEED_10 (0x2 << 2)
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#define EMAC_CTL0_SPEED_100 (0x3 << 2)
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#define EMAC_CTL0_SPEED_1000 (0x0 << 2)
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#define EMAC_CTL1 0x04
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#define EMAC_CTL1_SOFT_RST BIT(0)
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#define EMAC_CTL1_BURST_LEN_SHIFT 24
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#define EMAC_INT_STA 0x08
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#define EMAC_INT_EN 0x0c
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#define EMAC_TX_CTL0 0x10
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#define EMAC_TX_CTL0_TX_EN BIT(31)
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#define EMAC_TX_CTL1 0x14
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#define EMAC_TX_CTL1_TX_MD BIT(1)
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#define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
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#define EMAC_TX_CTL1_TX_DMA_START BIT(31)
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#define EMAC_TX_FLOW_CTL 0x1c
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#define EMAC_TX_DMA_DESC 0x20
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#define EMAC_RX_CTL0 0x24
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#define EMAC_RX_CTL0_RX_EN BIT(31)
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#define EMAC_RX_CTL1 0x28
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#define EMAC_RX_CTL1_RX_MD BIT(1)
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#define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2)
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#define EMAC_RX_CTL1_RX_ERR_FRM BIT(3)
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#define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
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#define EMAC_RX_CTL1_RX_DMA_START BIT(31)
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#define EMAC_RX_DMA_DESC 0x34
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#define EMAC_MII_CMD 0x48
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#define EMAC_MII_DATA 0x4c
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#define EMAC_ADDR0_HIGH 0x50
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#define EMAC_ADDR0_LOW 0x54
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#define EMAC_TX_DMA_STA 0xb0
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#define EMAC_TX_CUR_DESC 0xb4
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#define EMAC_TX_CUR_BUF 0xb8
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#define EMAC_RX_DMA_STA 0xc0
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#define EMAC_RX_CUR_DESC 0xc4
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#define EMAC_DESC_OWN_DMA BIT(31)
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#define EMAC_DESC_LAST_DESC BIT(30)
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#define EMAC_DESC_FIRST_DESC BIT(29)
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#define EMAC_DESC_CHAIN_SECOND BIT(24)
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#define EMAC_DESC_RX_ERROR_MASK 0x400068db
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DECLARE_GLOBAL_DATA_PTR;
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struct emac_variant {
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uint syscon_offset;
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bool soc_has_internal_phy;
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bool support_rmii;
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};
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struct emac_dma_desc {
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u32 status;
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u32 ctl_size;
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u32 buf_addr;
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u32 next;
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} __aligned(ARCH_DMA_MINALIGN);
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struct emac_eth_dev {
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struct emac_dma_desc rx_chain[CFG_TX_DESCR_NUM];
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struct emac_dma_desc tx_chain[CFG_RX_DESCR_NUM];
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char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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u32 interface;
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u32 phyaddr;
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u32 link;
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u32 speed;
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u32 duplex;
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u32 phy_configured;
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u32 tx_currdescnum;
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u32 rx_currdescnum;
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u32 addr;
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u32 tx_slot;
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bool use_internal_phy;
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const struct emac_variant *variant;
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void *mac_reg;
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void *sysctl_reg;
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struct phy_device *phydev;
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struct mii_dev *bus;
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struct clk tx_clk;
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struct clk ephy_clk;
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struct reset_ctl tx_rst;
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struct reset_ctl ephy_rst;
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#if CONFIG_IS_ENABLED(DM_GPIO)
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struct gpio_desc reset_gpio;
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#endif
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};
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struct sun8i_eth_pdata {
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struct eth_pdata eth_pdata;
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u32 reset_delays[3];
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int tx_delay_ps;
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int rx_delay_ps;
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};
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static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct udevice *dev = bus->priv;
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struct emac_eth_dev *priv = dev_get_priv(dev);
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u32 mii_cmd;
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int ret;
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mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_ADDR_MASK;
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/*
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* The EMAC clock is either 200 or 300 MHz, so we need a divider
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* of 128 to get the MDIO frequency below the required 2.5 MHz.
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*/
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if (!priv->use_internal_phy)
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mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
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MDIO_CMD_MII_CLK_CSR_SHIFT;
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mii_cmd |= MDIO_CMD_MII_BUSY;
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writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
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ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
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MDIO_CMD_MII_BUSY, false,
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CFG_MDIO_TIMEOUT, true);
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if (ret < 0)
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return ret;
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return readl(priv->mac_reg + EMAC_MII_DATA);
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}
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static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct udevice *dev = bus->priv;
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struct emac_eth_dev *priv = dev_get_priv(dev);
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u32 mii_cmd;
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mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_ADDR_MASK;
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/*
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* The EMAC clock is either 200 or 300 MHz, so we need a divider
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* of 128 to get the MDIO frequency below the required 2.5 MHz.
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*/
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if (!priv->use_internal_phy)
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mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
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MDIO_CMD_MII_CLK_CSR_SHIFT;
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mii_cmd |= MDIO_CMD_MII_WRITE;
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mii_cmd |= MDIO_CMD_MII_BUSY;
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writel(val, priv->mac_reg + EMAC_MII_DATA);
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writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
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return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
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MDIO_CMD_MII_BUSY, false,
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CFG_MDIO_TIMEOUT, true);
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}
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static int sun8i_eth_write_hwaddr(struct udevice *dev)
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{
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struct emac_eth_dev *priv = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_plat(dev);
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uchar *mac_id = pdata->enetaddr;
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u32 macid_lo, macid_hi;
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macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
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(mac_id[3] << 24);
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macid_hi = mac_id[4] + (mac_id[5] << 8);
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writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
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writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
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return 0;
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}
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static void sun8i_adjust_link(struct emac_eth_dev *priv,
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struct phy_device *phydev)
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{
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u32 v;
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v = readl(priv->mac_reg + EMAC_CTL0);
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if (phydev->duplex)
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v |= EMAC_CTL0_FULL_DUPLEX;
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else
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v &= ~EMAC_CTL0_FULL_DUPLEX;
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v &= ~EMAC_CTL0_SPEED_MASK;
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switch (phydev->speed) {
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case 1000:
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v |= EMAC_CTL0_SPEED_1000;
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break;
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case 100:
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v |= EMAC_CTL0_SPEED_100;
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break;
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case 10:
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v |= EMAC_CTL0_SPEED_10;
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break;
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}
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writel(v, priv->mac_reg + EMAC_CTL0);
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}
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static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
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{
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if (priv->use_internal_phy) {
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/* H3 based SoC's that has an Internal 100MBit PHY
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* needs to be configured and powered up before use
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*/
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reg &= ~H3_EPHY_DEFAULT_MASK;
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reg |= H3_EPHY_DEFAULT_VALUE;
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reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
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reg &= ~H3_EPHY_SHUTDOWN;
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return reg | H3_EPHY_SELECT;
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}
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/* This is to select External Gigabit PHY on those boards with
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* an internal PHY. Does not hurt on other SoCs. Linux does
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* it as well.
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*/
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return reg & ~H3_EPHY_SELECT;
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}
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static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
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struct emac_eth_dev *priv)
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{
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u32 reg;
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reg = readl(priv->sysctl_reg);
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reg = sun8i_emac_set_syscon_ephy(priv, reg);
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reg &= ~(SC_ETCS_MASK | SC_EPIT);
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if (priv->variant->support_rmii)
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reg &= ~SC_RMII_EN;
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switch (priv->interface) {
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case PHY_INTERFACE_MODE_MII:
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/* default */
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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reg |= SC_EPIT | SC_ETCS_INT_GMII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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if (priv->variant->support_rmii) {
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reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
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break;
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}
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default:
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debug("%s: Invalid PHY interface\n", __func__);
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return -EINVAL;
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}
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if (pdata->tx_delay_ps)
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reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
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& SC_ETXDC_MASK;
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if (pdata->rx_delay_ps)
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reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
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& SC_ERXDC_MASK;
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writel(reg, priv->sysctl_reg);
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return 0;
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}
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static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
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{
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struct phy_device *phydev;
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phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
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if (!phydev)
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return -ENODEV;
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priv->phydev = phydev;
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phy_config(priv->phydev);
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return 0;
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}
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#define cache_clean_descriptor(desc) \
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flush_dcache_range((uintptr_t)(desc), \
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(uintptr_t)(desc) + sizeof(struct emac_dma_desc))
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#define cache_inv_descriptor(desc) \
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invalidate_dcache_range((uintptr_t)(desc), \
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(uintptr_t)(desc) + sizeof(struct emac_dma_desc))
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static void rx_descs_init(struct emac_eth_dev *priv)
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{
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struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
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char *rxbuffs = &priv->rxbuffer[0];
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struct emac_dma_desc *desc_p;
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int i;
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/*
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* Make sure we don't have dirty cache lines around, which could
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* be cleaned to DRAM *after* the MAC has already written data to it.
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*/
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invalidate_dcache_range((uintptr_t)desc_table_p,
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(uintptr_t)desc_table_p + sizeof(priv->rx_chain));
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invalidate_dcache_range((uintptr_t)rxbuffs,
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(uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
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for (i = 0; i < CFG_RX_DESCR_NUM; i++) {
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desc_p = &desc_table_p[i];
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desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CFG_ETH_BUFSIZE];
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desc_p->next = (uintptr_t)&desc_table_p[i + 1];
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desc_p->ctl_size = CFG_ETH_RXSIZE;
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desc_p->status = EMAC_DESC_OWN_DMA;
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}
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/* Correcting the last pointer of the chain */
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desc_p->next = (uintptr_t)&desc_table_p[0];
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flush_dcache_range((uintptr_t)priv->rx_chain,
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(uintptr_t)priv->rx_chain +
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sizeof(priv->rx_chain));
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writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
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priv->rx_currdescnum = 0;
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}
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static void tx_descs_init(struct emac_eth_dev *priv)
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{
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struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
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char *txbuffs = &priv->txbuffer[0];
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struct emac_dma_desc *desc_p;
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int i;
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for (i = 0; i < CFG_TX_DESCR_NUM; i++) {
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desc_p = &desc_table_p[i];
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desc_p->buf_addr = (uintptr_t)&txbuffs[i * CFG_ETH_BUFSIZE];
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desc_p->next = (uintptr_t)&desc_table_p[i + 1];
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desc_p->ctl_size = 0;
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desc_p->status = 0;
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}
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/* Correcting the last pointer of the chain */
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desc_p->next = (uintptr_t)&desc_table_p[0];
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/* Flush the first TX buffer descriptor we will tell the MAC about. */
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cache_clean_descriptor(desc_table_p);
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writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
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priv->tx_currdescnum = 0;
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}
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static int sun8i_emac_eth_start(struct udevice *dev)
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{
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struct emac_eth_dev *priv = dev_get_priv(dev);
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int ret;
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/* Soft reset MAC */
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writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
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ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
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EMAC_CTL1_SOFT_RST, false, 10, true);
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|
if (ret) {
|
|
printf("%s: Timeout\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
/* Rewrite mac address after reset */
|
|
sun8i_eth_write_hwaddr(dev);
|
|
|
|
/* transmission starts after the full frame arrived in TX DMA FIFO */
|
|
setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
|
|
|
|
/*
|
|
* RX DMA reads data from RX DMA FIFO to host memory after a
|
|
* complete frame has been written to RX DMA FIFO
|
|
*/
|
|
setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
|
|
|
|
/* DMA burst length */
|
|
writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
|
|
|
|
/* Initialize rx/tx descriptors */
|
|
rx_descs_init(priv);
|
|
tx_descs_init(priv);
|
|
|
|
/* PHY Start Up */
|
|
ret = phy_startup(priv->phydev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
sun8i_adjust_link(priv, priv->phydev);
|
|
|
|
/* Start RX/TX DMA */
|
|
setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
|
|
EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
|
|
setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
|
|
|
|
/* Enable RX/TX */
|
|
setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
|
|
setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
u32 status, desc_num = priv->rx_currdescnum;
|
|
struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
|
|
uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
|
|
int length;
|
|
|
|
/* Invalidate entire buffer descriptor */
|
|
cache_inv_descriptor(desc_p);
|
|
|
|
status = desc_p->status;
|
|
|
|
/* Check for DMA own bit */
|
|
if (status & EMAC_DESC_OWN_DMA)
|
|
return -EAGAIN;
|
|
|
|
length = (status >> 16) & 0x3fff;
|
|
|
|
/* make sure we read from DRAM, not our cache */
|
|
invalidate_dcache_range(data_start,
|
|
data_start + roundup(length, ARCH_DMA_MINALIGN));
|
|
|
|
if (status & EMAC_DESC_RX_ERROR_MASK) {
|
|
debug("RX: packet error: 0x%x\n",
|
|
status & EMAC_DESC_RX_ERROR_MASK);
|
|
return 0;
|
|
}
|
|
if (length < 0x40) {
|
|
debug("RX: Bad Packet (runt)\n");
|
|
return 0;
|
|
}
|
|
|
|
if (length > CFG_ETH_RXSIZE) {
|
|
debug("RX: Too large packet (%d bytes)\n", length);
|
|
return 0;
|
|
}
|
|
|
|
*packetp = (uchar *)(ulong)desc_p->buf_addr;
|
|
|
|
return length;
|
|
}
|
|
|
|
static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
u32 desc_num = priv->tx_currdescnum;
|
|
struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
|
|
uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
|
|
uintptr_t data_end = data_start +
|
|
roundup(length, ARCH_DMA_MINALIGN);
|
|
|
|
desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
|
|
|
|
memcpy((void *)data_start, packet, length);
|
|
|
|
/* Flush data to be sent */
|
|
flush_dcache_range(data_start, data_end);
|
|
|
|
/* frame begin and end */
|
|
desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
|
|
desc_p->status = EMAC_DESC_OWN_DMA;
|
|
|
|
/* make sure the MAC reads the actual data from DRAM */
|
|
cache_clean_descriptor(desc_p);
|
|
|
|
/* Move to next Descriptor and wrap around */
|
|
if (++desc_num >= CFG_TX_DESCR_NUM)
|
|
desc_num = 0;
|
|
priv->tx_currdescnum = desc_num;
|
|
|
|
/* Start the DMA */
|
|
setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
|
|
|
|
/*
|
|
* Since we copied the data above, we return here without waiting
|
|
* for the packet to be actually send out.
|
|
*/
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sun8i_emac_board_setup(struct udevice *dev,
|
|
struct emac_eth_dev *priv)
|
|
{
|
|
int ret;
|
|
|
|
ret = clk_enable(&priv->tx_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable TX clock\n");
|
|
return ret;
|
|
}
|
|
|
|
if (reset_valid(&priv->tx_rst)) {
|
|
ret = reset_deassert(&priv->tx_rst);
|
|
if (ret) {
|
|
dev_err(dev, "failed to deassert TX reset\n");
|
|
goto err_tx_clk;
|
|
}
|
|
}
|
|
|
|
/* Only H3/H5 have clock controls for internal EPHY */
|
|
if (clk_valid(&priv->ephy_clk)) {
|
|
ret = clk_enable(&priv->ephy_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable EPHY TX clock\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (reset_valid(&priv->ephy_rst)) {
|
|
ret = reset_deassert(&priv->ephy_rst);
|
|
if (ret) {
|
|
dev_err(dev, "failed to deassert EPHY TX clock\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_tx_clk:
|
|
clk_disable(&priv->tx_clk);
|
|
return ret;
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(DM_GPIO)
|
|
static int sun8i_mdio_reset(struct mii_dev *bus)
|
|
{
|
|
struct udevice *dev = bus->priv;
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
|
|
int ret;
|
|
|
|
if (!dm_gpio_is_valid(&priv->reset_gpio))
|
|
return 0;
|
|
|
|
/* reset the phy */
|
|
ret = dm_gpio_set_value(&priv->reset_gpio, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
udelay(pdata->reset_delays[0]);
|
|
|
|
ret = dm_gpio_set_value(&priv->reset_gpio, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
udelay(pdata->reset_delays[1]);
|
|
|
|
ret = dm_gpio_set_value(&priv->reset_gpio, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
udelay(pdata->reset_delays[2]);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int sun8i_mdio_init(const char *name, struct udevice *priv)
|
|
{
|
|
struct mii_dev *bus = mdio_alloc();
|
|
|
|
if (!bus) {
|
|
debug("Failed to allocate MDIO bus\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
bus->read = sun8i_mdio_read;
|
|
bus->write = sun8i_mdio_write;
|
|
snprintf(bus->name, sizeof(bus->name), name);
|
|
bus->priv = (void *)priv;
|
|
#if CONFIG_IS_ENABLED(DM_GPIO)
|
|
bus->reset = sun8i_mdio_reset;
|
|
#endif
|
|
|
|
return mdio_register(bus);
|
|
}
|
|
|
|
static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
|
|
int length)
|
|
{
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
u32 desc_num = priv->rx_currdescnum;
|
|
struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
|
|
|
|
/* give the current descriptor back to the MAC */
|
|
desc_p->status |= EMAC_DESC_OWN_DMA;
|
|
|
|
/* Flush Status field of descriptor */
|
|
cache_clean_descriptor(desc_p);
|
|
|
|
/* Move to next desc and wrap-around condition. */
|
|
if (++desc_num >= CFG_RX_DESCR_NUM)
|
|
desc_num = 0;
|
|
priv->rx_currdescnum = desc_num;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sun8i_emac_eth_stop(struct udevice *dev)
|
|
{
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
/* Stop Rx/Tx transmitter */
|
|
clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
|
|
clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
|
|
|
|
/* Stop RX/TX DMA */
|
|
clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
|
|
clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
|
|
|
|
phy_shutdown(priv->phydev);
|
|
}
|
|
|
|
static int sun8i_emac_eth_probe(struct udevice *dev)
|
|
{
|
|
struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
|
|
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
priv->mac_reg = (void *)pdata->iobase;
|
|
|
|
ret = sun8i_emac_board_setup(dev, priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
sun8i_emac_set_syscon(sun8i_pdata, priv);
|
|
|
|
sun8i_mdio_init(dev->name, dev);
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
return sun8i_phy_init(priv, dev);
|
|
}
|
|
|
|
static const struct eth_ops sun8i_emac_eth_ops = {
|
|
.start = sun8i_emac_eth_start,
|
|
.write_hwaddr = sun8i_eth_write_hwaddr,
|
|
.send = sun8i_emac_eth_send,
|
|
.recv = sun8i_emac_eth_recv,
|
|
.free_pkt = sun8i_eth_free_pkt,
|
|
.stop = sun8i_emac_eth_stop,
|
|
};
|
|
|
|
static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
|
|
{
|
|
struct ofnode_phandle_args phandle;
|
|
int ret;
|
|
|
|
ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
|
|
NULL, 0, 0, &phandle);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* If the PHY node is not a child of the internal MDIO bus, we are
|
|
* using some external PHY.
|
|
*/
|
|
if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
|
|
"allwinner,sun8i-h3-mdio-internal"))
|
|
return 0;
|
|
|
|
ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get EPHY TX clock\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get EPHY TX reset\n");
|
|
return ret;
|
|
}
|
|
|
|
priv->use_internal_phy = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
|
|
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
phys_addr_t syscon_base;
|
|
const fdt32_t *reg;
|
|
int node = dev_of_offset(dev);
|
|
int offset = 0;
|
|
#if CONFIG_IS_ENABLED(DM_GPIO)
|
|
int reset_flags = GPIOD_IS_OUT;
|
|
#endif
|
|
int ret;
|
|
|
|
pdata->iobase = dev_read_addr(dev);
|
|
if (pdata->iobase == FDT_ADDR_T_NONE) {
|
|
debug("%s: Cannot find MAC base address\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->variant = (const void *)dev_get_driver_data(dev);
|
|
|
|
if (!priv->variant) {
|
|
printf("%s: Missing variant\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get TX clock\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
|
|
if (ret && ret != -ENOENT) {
|
|
dev_err(dev, "failed to get TX reset\n");
|
|
return ret;
|
|
}
|
|
|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
|
|
if (offset < 0) {
|
|
debug("%s: cannot find syscon node\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
|
|
if (!reg) {
|
|
debug("%s: cannot find reg property in syscon node\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg);
|
|
if (syscon_base == FDT_ADDR_T_NONE) {
|
|
debug("%s: Cannot find syscon base address\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->sysctl_reg = (void *)syscon_base + priv->variant->syscon_offset;
|
|
|
|
pdata->phy_interface = -1;
|
|
priv->phyaddr = -1;
|
|
priv->use_internal_phy = false;
|
|
|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
|
|
if (offset < 0) {
|
|
debug("%s: Cannot find PHY address\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
|
|
|
|
pdata->phy_interface = dev_read_phy_mode(dev);
|
|
debug("phy interface %d\n", pdata->phy_interface);
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
|
|
return -EINVAL;
|
|
|
|
if (priv->variant->soc_has_internal_phy) {
|
|
ret = sun8i_handle_internal_phy(dev, priv);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
priv->interface = pdata->phy_interface;
|
|
|
|
sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
|
|
"allwinner,tx-delay-ps", 0);
|
|
if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
|
|
printf("%s: Invalid TX delay value %d\n", __func__,
|
|
sun8i_pdata->tx_delay_ps);
|
|
|
|
sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
|
|
"allwinner,rx-delay-ps", 0);
|
|
if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
|
|
printf("%s: Invalid RX delay value %d\n", __func__,
|
|
sun8i_pdata->rx_delay_ps);
|
|
|
|
#if CONFIG_IS_ENABLED(DM_GPIO)
|
|
if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
|
|
"snps,reset-active-low"))
|
|
reset_flags |= GPIOD_ACTIVE_LOW;
|
|
|
|
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
|
|
&priv->reset_gpio, reset_flags);
|
|
|
|
if (ret == 0) {
|
|
ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
|
|
"snps,reset-delays-us",
|
|
sun8i_pdata->reset_delays, 3);
|
|
} else if (ret == -ENOENT) {
|
|
ret = 0;
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct emac_variant emac_variant_a83t = {
|
|
.syscon_offset = 0x30,
|
|
};
|
|
|
|
static const struct emac_variant emac_variant_h3 = {
|
|
.syscon_offset = 0x30,
|
|
.soc_has_internal_phy = true,
|
|
.support_rmii = true,
|
|
};
|
|
|
|
static const struct emac_variant emac_variant_r40 = {
|
|
.syscon_offset = 0x164,
|
|
};
|
|
|
|
static const struct emac_variant emac_variant_a64 = {
|
|
.syscon_offset = 0x30,
|
|
.support_rmii = true,
|
|
};
|
|
|
|
static const struct emac_variant emac_variant_h6 = {
|
|
.syscon_offset = 0x30,
|
|
.support_rmii = true,
|
|
};
|
|
|
|
static const struct udevice_id sun8i_emac_eth_ids[] = {
|
|
{ .compatible = "allwinner,sun8i-a83t-emac",
|
|
.data = (ulong)&emac_variant_a83t },
|
|
{ .compatible = "allwinner,sun8i-h3-emac",
|
|
.data = (ulong)&emac_variant_h3 },
|
|
{ .compatible = "allwinner,sun8i-r40-gmac",
|
|
.data = (ulong)&emac_variant_r40 },
|
|
{ .compatible = "allwinner,sun50i-a64-emac",
|
|
.data = (ulong)&emac_variant_a64 },
|
|
{ .compatible = "allwinner,sun50i-h6-emac",
|
|
.data = (ulong)&emac_variant_h6 },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_sun8i_emac) = {
|
|
.name = "eth_sun8i_emac",
|
|
.id = UCLASS_ETH,
|
|
.of_match = sun8i_emac_eth_ids,
|
|
.of_to_plat = sun8i_emac_eth_of_to_plat,
|
|
.probe = sun8i_emac_eth_probe,
|
|
.ops = &sun8i_emac_eth_ops,
|
|
.priv_auto = sizeof(struct emac_eth_dev),
|
|
.plat_auto = sizeof(struct sun8i_eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|