mirror of
https://github.com/AsahiLinux/u-boot
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97148cb614
Perform a simple rename of CONFIG_SH_ETHER_USE_PORT to CFG_SH_ETHER_USE_PORT Signed-off-by: Tom Rini <trini@konsulko.com>
886 lines
22 KiB
C
886 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* sh_eth.c - Driver for Renesas ethernet controller.
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*
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* Copyright (C) 2008, 2011 Renesas Solutions Corp.
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* Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
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* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
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* Copyright (C) 2013, 2014 Renesas Electronics Corporation
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*/
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#include <config.h>
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#include <common.h>
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#include <cpu_func.h>
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#include <env.h>
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#include <log.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/cache.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <linux/mii.h>
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#include <asm/gpio.h>
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#include "sh_eth.h"
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#ifndef CFG_SH_ETHER_USE_PORT
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# error "Please define CFG_SH_ETHER_USE_PORT"
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#endif
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#ifndef CFG_SH_ETHER_PHY_ADDR
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# error "Please define CFG_SH_ETHER_PHY_ADDR"
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#endif
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#if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \
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!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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#define flush_cache_wback(addr, len) \
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flush_dcache_range((unsigned long)addr, \
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(unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE)))
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#else
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#define flush_cache_wback(...)
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#endif
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#if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
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#define invalidate_cache(addr, len) \
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{ \
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unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \
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unsigned long start, end; \
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\
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start = (unsigned long)addr; \
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end = start + len; \
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start &= ~(line_size - 1); \
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end = ((end + line_size - 1) & ~(line_size - 1)); \
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\
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invalidate_dcache_range(start, end); \
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}
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#else
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#define invalidate_cache(...)
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#endif
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#define TIMEOUT_CNT 1000
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static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
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{
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int ret = 0, timeout;
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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if (!packet || len > 0xffff) {
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printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
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ret = -EINVAL;
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goto err;
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}
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/* packet must be a 4 byte boundary */
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if ((uintptr_t)packet & 3) {
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printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
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, __func__);
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ret = -EFAULT;
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goto err;
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}
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/* Update tx descriptor */
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flush_cache_wback(packet, len);
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port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
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port_info->tx_desc_cur->td1 = len << 16;
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/* Must preserve the end of descriptor list indication */
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if (port_info->tx_desc_cur->td0 & TD_TDLE)
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port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
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else
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port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
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flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
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/* Restart the transmitter if disabled */
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if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
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sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
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/* Wait until packet is transmitted */
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timeout = TIMEOUT_CNT;
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do {
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invalidate_cache(port_info->tx_desc_cur,
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sizeof(struct tx_desc_s));
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udelay(100);
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} while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
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if (timeout < 0) {
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printf(SHETHER_NAME ": transmit timeout\n");
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ret = -ETIMEDOUT;
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goto err;
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}
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port_info->tx_desc_cur++;
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if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
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port_info->tx_desc_cur = port_info->tx_desc_base;
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err:
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return ret;
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}
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static int sh_eth_recv_start(struct sh_eth_dev *eth)
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{
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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/* Check if the rx descriptor is ready */
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invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
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if (port_info->rx_desc_cur->rd0 & RD_RACT)
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return -EINVAL;
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/* Check for errors */
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if (port_info->rx_desc_cur->rd0 & RD_RFE)
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return -EINVAL;
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return port_info->rx_desc_cur->rd1 & 0xffff;
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}
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static void sh_eth_recv_finish(struct sh_eth_dev *eth)
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{
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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/* Make current descriptor available again */
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if (port_info->rx_desc_cur->rd0 & RD_RDLE)
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port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
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else
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port_info->rx_desc_cur->rd0 = RD_RACT;
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flush_cache_wback(port_info->rx_desc_cur,
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sizeof(struct rx_desc_s));
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/* Point to the next descriptor */
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port_info->rx_desc_cur++;
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if (port_info->rx_desc_cur >=
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port_info->rx_desc_base + NUM_RX_DESC)
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port_info->rx_desc_cur = port_info->rx_desc_base;
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}
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static int sh_eth_reset(struct sh_eth_dev *eth)
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{
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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int ret = 0, i;
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/* Start e-dmac transmitter and receiver */
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sh_eth_write(port_info, EDSR_ENALL, EDSR);
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/* Perform a software reset and wait for it to complete */
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sh_eth_write(port_info, EDMR_SRST, EDMR);
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for (i = 0; i < TIMEOUT_CNT; i++) {
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if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
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break;
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udelay(1000);
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}
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if (i == TIMEOUT_CNT) {
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printf(SHETHER_NAME ": Software reset timeout\n");
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ret = -EIO;
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}
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return ret;
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#else
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sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
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mdelay(3);
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sh_eth_write(port_info,
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sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
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return 0;
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#endif
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}
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static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
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{
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int i, ret = 0;
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u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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struct tx_desc_s *cur_tx_desc;
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/*
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* Allocate rx descriptors. They must be aligned to size of struct
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* tx_desc_s.
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*/
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port_info->tx_desc_alloc =
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memalign(sizeof(struct tx_desc_s), alloc_desc_size);
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if (!port_info->tx_desc_alloc) {
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printf(SHETHER_NAME ": memalign failed\n");
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ret = -ENOMEM;
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goto err;
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}
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flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
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/* Make sure we use a P2 address (non-cacheable) */
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port_info->tx_desc_base =
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(struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
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port_info->tx_desc_cur = port_info->tx_desc_base;
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/* Initialize all descriptors */
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for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
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cur_tx_desc++, i++) {
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cur_tx_desc->td0 = 0x00;
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cur_tx_desc->td1 = 0x00;
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cur_tx_desc->td2 = 0x00;
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}
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/* Mark the end of the descriptors */
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cur_tx_desc--;
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cur_tx_desc->td0 |= TD_TDLE;
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/*
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* Point the controller to the tx descriptor list. Must use physical
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* addresses
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*/
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sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
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sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
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sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
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#endif
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err:
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return ret;
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}
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static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
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{
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int i, ret = 0;
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u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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struct rx_desc_s *cur_rx_desc;
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u8 *rx_buf;
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/*
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* Allocate rx descriptors. They must be aligned to size of struct
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* rx_desc_s.
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*/
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port_info->rx_desc_alloc =
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memalign(sizeof(struct rx_desc_s), alloc_desc_size);
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if (!port_info->rx_desc_alloc) {
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printf(SHETHER_NAME ": memalign failed\n");
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ret = -ENOMEM;
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goto err;
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}
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flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
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/* Make sure we use a P2 address (non-cacheable) */
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port_info->rx_desc_base =
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(struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
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port_info->rx_desc_cur = port_info->rx_desc_base;
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/*
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* Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
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* aligned and in P2 area.
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*/
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port_info->rx_buf_alloc =
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memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
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if (!port_info->rx_buf_alloc) {
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printf(SHETHER_NAME ": alloc failed\n");
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ret = -ENOMEM;
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goto err_buf_alloc;
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}
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port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
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/* Initialize all descriptors */
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for (cur_rx_desc = port_info->rx_desc_base,
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rx_buf = port_info->rx_buf_base, i = 0;
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i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
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cur_rx_desc->rd0 = RD_RACT;
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cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
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cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
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}
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/* Mark the end of the descriptors */
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cur_rx_desc--;
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cur_rx_desc->rd0 |= RD_RDLE;
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/* Point the controller to the rx descriptor list */
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sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
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sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
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sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
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#endif
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return ret;
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err_buf_alloc:
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free(port_info->rx_desc_alloc);
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port_info->rx_desc_alloc = NULL;
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err:
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return ret;
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}
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static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
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{
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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if (port_info->tx_desc_alloc) {
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free(port_info->tx_desc_alloc);
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port_info->tx_desc_alloc = NULL;
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}
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}
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static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
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{
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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if (port_info->rx_desc_alloc) {
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free(port_info->rx_desc_alloc);
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port_info->rx_desc_alloc = NULL;
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}
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if (port_info->rx_buf_alloc) {
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free(port_info->rx_buf_alloc);
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port_info->rx_buf_alloc = NULL;
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}
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}
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static int sh_eth_desc_init(struct sh_eth_dev *eth)
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{
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int ret = 0;
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ret = sh_eth_tx_desc_init(eth);
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if (ret)
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goto err_tx_init;
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ret = sh_eth_rx_desc_init(eth);
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if (ret)
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goto err_rx_init;
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return ret;
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err_rx_init:
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sh_eth_tx_desc_free(eth);
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err_tx_init:
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return ret;
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}
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static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
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unsigned char *mac)
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{
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u32 val;
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val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
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sh_eth_write(port_info, val, MAHR);
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val = (mac[4] << 8) | mac[5];
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sh_eth_write(port_info, val, MALR);
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}
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static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
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{
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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unsigned long edmr;
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/* Configure e-dmac registers */
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edmr = sh_eth_read(port_info, EDMR);
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edmr &= ~EMDR_DESC_R;
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edmr |= EMDR_DESC | EDMR_EL;
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#if defined(CONFIG_R8A77980)
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edmr |= EDMR_NBST;
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#endif
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sh_eth_write(port_info, edmr, EDMR);
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sh_eth_write(port_info, 0, EESIPR);
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sh_eth_write(port_info, 0, TRSCER);
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sh_eth_write(port_info, 0, TFTR);
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sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
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sh_eth_write(port_info, RMCR_RST, RMCR);
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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sh_eth_write(port_info, 0, RPADIR);
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#endif
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sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
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/* Configure e-mac registers */
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sh_eth_write(port_info, 0, ECSIPR);
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/* Set Mac address */
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sh_eth_write_hwaddr(port_info, mac);
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sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
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#if defined(SH_ETH_TYPE_GETHER)
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sh_eth_write(port_info, 0, PIPR);
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#endif
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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sh_eth_write(port_info, APR_AP, APR);
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sh_eth_write(port_info, MPR_MP, MPR);
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sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
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#endif
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#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
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sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
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#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
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sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
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#endif
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}
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static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
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{
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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struct phy_device *phy = port_info->phydev;
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int ret = 0;
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u32 val = 0;
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/* Set the transfer speed */
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if (phy->speed == 100) {
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printf(SHETHER_NAME ": 100Base/");
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#if defined(SH_ETH_TYPE_GETHER)
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sh_eth_write(port_info, GECMR_100B, GECMR);
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#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
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sh_eth_write(port_info, 1, RTRATE);
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#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
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val = ECMR_RTM;
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#endif
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} else if (phy->speed == 10) {
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printf(SHETHER_NAME ": 10Base/");
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#if defined(SH_ETH_TYPE_GETHER)
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sh_eth_write(port_info, GECMR_10B, GECMR);
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#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
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sh_eth_write(port_info, 0, RTRATE);
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#endif
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}
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#if defined(SH_ETH_TYPE_GETHER)
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else if (phy->speed == 1000) {
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printf(SHETHER_NAME ": 1000Base/");
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sh_eth_write(port_info, GECMR_1000B, GECMR);
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}
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#endif
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/* Check if full duplex mode is supported by the phy */
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if (phy->duplex) {
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printf("Full\n");
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sh_eth_write(port_info,
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val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
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ECMR);
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} else {
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printf("Half\n");
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|
sh_eth_write(port_info,
|
|
val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
|
|
ECMR);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void sh_eth_start(struct sh_eth_dev *eth)
|
|
{
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
/*
|
|
* Enable the e-dmac receiver only. The transmitter will be enabled when
|
|
* we have something to transmit
|
|
*/
|
|
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
|
}
|
|
|
|
static void sh_eth_stop(struct sh_eth_dev *eth)
|
|
{
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
sh_eth_write(port_info, ~EDRRR_R, EDRRR);
|
|
}
|
|
|
|
static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
|
|
{
|
|
int ret = 0;
|
|
|
|
ret = sh_eth_reset(eth);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = sh_eth_desc_init(eth);
|
|
if (ret)
|
|
return ret;
|
|
|
|
sh_eth_mac_regs_config(eth, mac);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_start_common(struct sh_eth_dev *eth)
|
|
{
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
int ret;
|
|
|
|
ret = phy_startup(port_info->phydev);
|
|
if (ret) {
|
|
printf(SHETHER_NAME ": phy startup failure\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = sh_eth_phy_regs_config(eth);
|
|
if (ret)
|
|
return ret;
|
|
|
|
sh_eth_start(eth);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct sh_ether_priv {
|
|
struct sh_eth_dev shdev;
|
|
|
|
struct mii_dev *bus;
|
|
phys_addr_t iobase;
|
|
struct clk clk;
|
|
struct gpio_desc reset_gpio;
|
|
};
|
|
|
|
static int sh_ether_send(struct udevice *dev, void *packet, int len)
|
|
{
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
|
|
return sh_eth_send_common(eth, packet, len);
|
|
}
|
|
|
|
static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
|
|
int len;
|
|
|
|
len = sh_eth_recv_start(eth);
|
|
if (len > 0) {
|
|
invalidate_cache(packet, len);
|
|
*packetp = packet;
|
|
|
|
return len;
|
|
} else {
|
|
len = 0;
|
|
|
|
/* Restart the receiver if disabled */
|
|
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
|
|
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
|
|
|
return -EAGAIN;
|
|
}
|
|
}
|
|
|
|
static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
{
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
sh_eth_recv_finish(eth);
|
|
|
|
/* Restart the receiver if disabled */
|
|
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
|
|
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_ether_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
|
|
sh_eth_write_hwaddr(port_info, pdata->enetaddr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_phy_config(struct udevice *dev)
|
|
{
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
int ret = 0;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
struct phy_device *phydev;
|
|
int mask = 0xffffffff;
|
|
|
|
phydev = phy_find_by_mask(priv->bus, mask);
|
|
if (!phydev)
|
|
return -ENODEV;
|
|
|
|
phy_connect_dev(phydev, dev, pdata->phy_interface);
|
|
|
|
port_info->phydev = phydev;
|
|
phy_config(phydev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sh_ether_start(struct udevice *dev)
|
|
{
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
int ret;
|
|
|
|
ret = sh_eth_init_common(eth, pdata->enetaddr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = sh_eth_start_common(eth);
|
|
if (ret)
|
|
goto err_start;
|
|
|
|
return 0;
|
|
|
|
err_start:
|
|
sh_eth_tx_desc_free(eth);
|
|
sh_eth_rx_desc_free(eth);
|
|
return ret;
|
|
}
|
|
|
|
static void sh_ether_stop(struct udevice *dev)
|
|
{
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
phy_shutdown(port_info->phydev);
|
|
sh_eth_stop(&priv->shdev);
|
|
}
|
|
|
|
static int sh_ether_probe(struct udevice *udev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(udev);
|
|
struct sh_ether_priv *priv = dev_get_priv(udev);
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
struct ofnode_phandle_args phandle_args;
|
|
struct mii_dev *mdiodev;
|
|
int ret;
|
|
|
|
priv->iobase = pdata->iobase;
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
ret = clk_get_by_index(udev, 0, &priv->clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
#endif
|
|
|
|
ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
|
|
if (!ret) {
|
|
gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
|
|
&priv->reset_gpio, GPIOD_IS_OUT);
|
|
}
|
|
|
|
if (!dm_gpio_is_valid(&priv->reset_gpio)) {
|
|
gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
|
|
GPIOD_IS_OUT);
|
|
}
|
|
|
|
mdiodev = mdio_alloc();
|
|
if (!mdiodev) {
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
|
|
mdiodev->read = bb_miiphy_read;
|
|
mdiodev->write = bb_miiphy_write;
|
|
bb_miiphy_buses[0].priv = eth;
|
|
snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
|
|
|
|
ret = mdio_register(mdiodev);
|
|
if (ret < 0)
|
|
goto err_mdio_register;
|
|
|
|
priv->bus = miiphy_get_dev_by_name(udev->name);
|
|
|
|
eth->port = CFG_SH_ETHER_USE_PORT;
|
|
eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
|
|
eth->port_info[eth->port].iobase =
|
|
(void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
ret = clk_enable(&priv->clk);
|
|
if (ret)
|
|
goto err_mdio_register;
|
|
#endif
|
|
|
|
ret = sh_eth_init_common(eth, pdata->enetaddr);
|
|
if (ret)
|
|
goto err_phy_config;
|
|
|
|
ret = sh_eth_phy_config(udev);
|
|
if (ret) {
|
|
printf(SHETHER_NAME ": phy config timeout\n");
|
|
goto err_phy_config;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_phy_config:
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
clk_disable(&priv->clk);
|
|
#endif
|
|
err_mdio_register:
|
|
mdio_free(mdiodev);
|
|
return ret;
|
|
}
|
|
|
|
static int sh_ether_remove(struct udevice *udev)
|
|
{
|
|
struct sh_ether_priv *priv = dev_get_priv(udev);
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
clk_disable(&priv->clk);
|
|
#endif
|
|
free(port_info->phydev);
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
if (dm_gpio_is_valid(&priv->reset_gpio))
|
|
dm_gpio_free(udev, &priv->reset_gpio);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops sh_ether_ops = {
|
|
.start = sh_ether_start,
|
|
.send = sh_ether_send,
|
|
.recv = sh_ether_recv,
|
|
.free_pkt = sh_ether_free_pkt,
|
|
.stop = sh_ether_stop,
|
|
.write_hwaddr = sh_ether_write_hwaddr,
|
|
};
|
|
|
|
int sh_ether_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
const fdt32_t *cell;
|
|
|
|
pdata->iobase = dev_read_addr(dev);
|
|
|
|
pdata->phy_interface = dev_read_phy_mode(dev);
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
|
|
return -EINVAL;
|
|
|
|
pdata->max_speed = 1000;
|
|
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
|
|
if (cell)
|
|
pdata->max_speed = fdt32_to_cpu(*cell);
|
|
|
|
sprintf(bb_miiphy_buses[0].name, dev->name);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id sh_ether_ids[] = {
|
|
{ .compatible = "renesas,ether-r7s72100" },
|
|
{ .compatible = "renesas,ether-r8a7790" },
|
|
{ .compatible = "renesas,ether-r8a7791" },
|
|
{ .compatible = "renesas,ether-r8a7793" },
|
|
{ .compatible = "renesas,ether-r8a7794" },
|
|
{ .compatible = "renesas,gether-r8a77980" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_sh_ether) = {
|
|
.name = "sh_ether",
|
|
.id = UCLASS_ETH,
|
|
.of_match = sh_ether_ids,
|
|
.of_to_plat = sh_ether_of_to_plat,
|
|
.probe = sh_ether_probe,
|
|
.remove = sh_ether_remove,
|
|
.ops = &sh_ether_ops,
|
|
.priv_auto = sizeof(struct sh_ether_priv),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
|
|
/******* for bb_miiphy *******/
|
|
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
if (v)
|
|
sh_eth_write(port_info,
|
|
sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
|
|
else
|
|
sh_eth_write(port_info,
|
|
sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
*v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
|
|
{
|
|
struct sh_eth_dev *eth = bus->priv;
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
if (v)
|
|
sh_eth_write(port_info,
|
|
sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
|
|
else
|
|
sh_eth_write(port_info,
|
|
sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
|
|
{
|
|
udelay(10);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct bb_miiphy_bus bb_miiphy_buses[] = {
|
|
{
|
|
.name = "sh_eth",
|
|
.init = sh_eth_bb_init,
|
|
.mdio_active = sh_eth_bb_mdio_active,
|
|
.mdio_tristate = sh_eth_bb_mdio_tristate,
|
|
.set_mdio = sh_eth_bb_set_mdio,
|
|
.get_mdio = sh_eth_bb_get_mdio,
|
|
.set_mdc = sh_eth_bb_set_mdc,
|
|
.delay = sh_eth_bb_delay,
|
|
}
|
|
};
|
|
|
|
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
|