mirror of
https://github.com/AsahiLinux/u-boot
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f6fa0715ce
As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini <trini@konsulko.com>
667 lines
20 KiB
C
667 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* rtl8139.c : U-Boot driver for the RealTek RTL8139
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*
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* Masami Komiya (mkomiya@sonare.it)
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*
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* Most part is taken from rtl8139.c of etherboot
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*
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*/
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/* rtl8139.c - etherboot driver for the Realtek 8139 chipset
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*
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* ported from the linux driver written by Donald Becker
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* by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
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*
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* changes to the original driver:
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* - removed support for interrupts, switching to polling mode (yuck!)
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* - removed support for the 8129 chip (external MII)
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*/
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/*********************************************************************/
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/* Revision History */
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/*********************************************************************/
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/*
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* 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
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* Put in virt_to_bus calls to allow Etherboot relocation.
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*
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* 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
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* Following email from Hyun-Joon Cha, added a disable routine, otherwise
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* NIC remains live and can crash the kernel later.
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*
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* 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
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* Shuffled things around, removed the leftovers from the 8129 support
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* that was in the Linux driver and added a bit more 8139 definitions.
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* Moved the 8K receive buffer to a fixed, available address outside the
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* 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
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* way to make room for the Etherboot features that need substantial amounts
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* of code like the ANSI console support. Currently the buffer is just below
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* 0x10000, so this even conforms to the tagged boot image specification,
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* which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
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* interpretation of this "reserved" is that Etherboot may do whatever it
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* likes, as long as its environment is kept intact (like the BIOS
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* variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms
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* were that if Etherboot was left at the boot menu for several minutes, the
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* first eth_poll failed. Seems like I am the only person who does this.
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* First of all I fixed the debugging code and then set out for a long bug
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* hunting session. It took me about a week full time work - poking around
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* various places in the driver, reading Don Becker's and Jeff Garzik's Linux
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* driver and even the FreeBSD driver (what a piece of crap!) - and
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* eventually spotted the nasty thing: the transmit routine was acknowledging
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* each and every interrupt pending, including the RxOverrun and RxFIFIOver
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* interrupts. This confused the RTL8139 thoroughly. It destroyed the
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* Rx ring contents by dumping the 2K FIFO contents right where we wanted to
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* get the next packet. Oh well, what fun.
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*
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* 18 Jan 2000 mdc@thinguin.org (Marty Connor)
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* Drastically simplified error handling. Basically, if any error
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* in transmission or reception occurs, the card is reset.
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* Also, pointed all transmit descriptors to the same buffer to
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* save buffer space. This should decrease driver size and avoid
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* corruption because of exceeding 32K during runtime.
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*
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* 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
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* rtl8139_recv was quite broken: it used the RxOK interrupt flag instead
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* of the RxBufferEmpty flag which often resulted in very bad
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* transmission performace - below 1kBytes/s.
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*
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#define RTL_TIMEOUT 100000
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/* PCI Tuning Parameters */
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/* Threshold is bytes transferred to chip before transmission starts. */
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#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
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#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
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#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
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#define TX_DMA_BURST 4 /* Calculate as 16<<val. */
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#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
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#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
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#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
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#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
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#define DEBUG_TX 0 /* set to 1 to enable debug code */
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#define DEBUG_RX 0 /* set to 1 to enable debug code */
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#define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a))
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#define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a))
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/* Symbolic offsets to registers. */
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/* Ethernet hardware address. */
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#define RTL_REG_MAC0 0x00
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/* Multicast filter. */
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#define RTL_REG_MAR0 0x08
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/* Transmit status (four 32bit registers). */
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#define RTL_REG_TXSTATUS0 0x10
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/* Tx descriptors (also four 32bit). */
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#define RTL_REG_TXADDR0 0x20
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#define RTL_REG_RXBUF 0x30
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#define RTL_REG_RXEARLYCNT 0x34
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#define RTL_REG_RXEARLYSTATUS 0x36
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#define RTL_REG_CHIPCMD 0x37
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#define RTL_REG_CHIPCMD_CMDRESET BIT(4)
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#define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
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#define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
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#define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
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#define RTL_REG_RXBUFPTR 0x38
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#define RTL_REG_RXBUFADDR 0x3A
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#define RTL_REG_INTRMASK 0x3C
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#define RTL_REG_INTRSTATUS 0x3E
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#define RTL_REG_INTRSTATUS_PCIERR BIT(15)
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#define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
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#define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
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#define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
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#define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
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#define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
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#define RTL_REG_INTRSTATUS_TXERR BIT(3)
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#define RTL_REG_INTRSTATUS_TXOK BIT(2)
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#define RTL_REG_INTRSTATUS_RXERR BIT(1)
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#define RTL_REG_INTRSTATUS_RXOK BIT(0)
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#define RTL_REG_TXCONFIG 0x40
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#define RTL_REG_RXCONFIG 0x44
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#define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
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#define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
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#define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
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#define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
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#define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
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#define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
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#define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
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/* general-purpose counter. */
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#define RTL_REG_TIMER 0x48
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/* 24 bits valid, write clears. */
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#define RTL_REG_RXMISSED 0x4C
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#define RTL_REG_CFG9346 0x50
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#define RTL_REG_CONFIG0 0x51
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#define RTL_REG_CONFIG1 0x52
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/* intr if gp counter reaches this value */
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#define RTL_REG_TIMERINTRREG 0x54
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#define RTL_REG_MEDIASTATUS 0x58
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#define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
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#define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
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#define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
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#define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
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#define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
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#define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
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#define RTL_REG_CONFIG3 0x59
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#define RTL_REG_MULTIINTR 0x5C
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/* revision of the RTL8139 chip */
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#define RTL_REG_REVISIONID 0x5E
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#define RTL_REG_TXSUMMARY 0x60
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#define RTL_REG_MII_BMCR 0x62
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#define RTL_REG_MII_BMSR 0x64
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#define RTL_REG_NWAYADVERT 0x66
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#define RTL_REG_NWAYLPAR 0x68
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#define RTL_REG_NWAYEXPANSION 0x6A
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#define RTL_REG_DISCONNECTCNT 0x6C
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#define RTL_REG_FALSECARRIERCNT 0x6E
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#define RTL_REG_NWAYTESTREG 0x70
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/* packet received counter */
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#define RTL_REG_RXCNT 0x72
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/* chip status and configuration register */
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#define RTL_REG_CSCR 0x74
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#define RTL_REG_PHYPARM1 0x78
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#define RTL_REG_TWISTERPARM 0x7c
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/* undocumented */
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#define RTL_REG_PHYPARM2 0x80
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/*
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* from 0x84 onwards are a number of power management/wakeup frame
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* definitions we will probably never need to know about.
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*/
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#define RTL_STS_RXMULTICAST BIT(15)
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#define RTL_STS_RXPHYSICAL BIT(14)
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#define RTL_STS_RXBROADCAST BIT(13)
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#define RTL_STS_RXBADSYMBOL BIT(5)
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#define RTL_STS_RXRUNT BIT(4)
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#define RTL_STS_RXTOOLONG BIT(3)
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#define RTL_STS_RXCRCERR BIT(2)
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#define RTL_STS_RXBADALIGN BIT(1)
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#define RTL_STS_RXSTATUSOK BIT(0)
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struct rtl8139_priv {
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struct udevice *devno;
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unsigned int rxstatus;
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unsigned int cur_rx;
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unsigned int cur_tx;
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unsigned long ioaddr;
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unsigned char enetaddr[6];
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};
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/* The RTL8139 can only transmit from a contiguous, aligned memory block. */
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static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
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static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4);
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/* Serial EEPROM section. */
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/* EEPROM_Ctrl bits. */
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#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
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#define EE_CS 0x08 /* EEPROM chip select. */
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#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
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#define EE_WRITE_0 0x00
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#define EE_WRITE_1 0x02
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#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
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#define EE_ENB (0x80 | EE_CS)
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/* The EEPROM commands include the alway-set leading bit. */
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#define EE_WRITE_CMD 5
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#define EE_READ_CMD 6
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#define EE_ERASE_CMD 7
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static void rtl8139_eeprom_delay(struct rtl8139_priv *priv)
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{
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/*
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* Delay between EEPROM clock transitions.
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* No extra delay is needed with 33MHz PCI, but 66MHz may change this.
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*/
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inl(priv->ioaddr + RTL_REG_CFG9346);
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}
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static int rtl8139_read_eeprom(struct rtl8139_priv *priv,
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unsigned int location, unsigned int addr_len)
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{
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unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
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uintptr_t ee_addr = priv->ioaddr + RTL_REG_CFG9346;
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unsigned int retval = 0;
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u8 dataval;
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int i;
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outb(EE_ENB & ~EE_CS, ee_addr);
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outb(EE_ENB, ee_addr);
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rtl8139_eeprom_delay(priv);
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/* Shift the read command bits out. */
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for (i = 4 + addr_len; i >= 0; i--) {
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dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
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outb(EE_ENB | dataval, ee_addr);
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rtl8139_eeprom_delay(priv);
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outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
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rtl8139_eeprom_delay(priv);
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}
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outb(EE_ENB, ee_addr);
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rtl8139_eeprom_delay(priv);
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for (i = 16; i > 0; i--) {
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outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
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rtl8139_eeprom_delay(priv);
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retval <<= 1;
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retval |= inb(ee_addr) & EE_DATA_READ;
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outb(EE_ENB, ee_addr);
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rtl8139_eeprom_delay(priv);
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}
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/* Terminate the EEPROM access. */
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outb(~EE_CS, ee_addr);
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rtl8139_eeprom_delay(priv);
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return retval;
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}
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static const unsigned int rtl8139_rx_config =
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(RX_BUF_LEN_IDX << 11) |
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(RX_FIFO_THRESH << 13) |
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(RX_DMA_BURST << 8);
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static void rtl8139_set_rx_mode(struct rtl8139_priv *priv)
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{
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/* !IFF_PROMISC */
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unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
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RTL_REG_RXCONFIG_ACCEPTMULTICAST |
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RTL_REG_RXCONFIG_ACCEPTMYPHYS;
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outl(rtl8139_rx_config | rx_mode, priv->ioaddr + RTL_REG_RXCONFIG);
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outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 0);
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outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 4);
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}
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static void rtl8139_hw_reset(struct rtl8139_priv *priv)
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{
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u8 reg;
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int i;
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outb(RTL_REG_CHIPCMD_CMDRESET, priv->ioaddr + RTL_REG_CHIPCMD);
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/* Give the chip 10ms to finish the reset. */
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for (i = 0; i < 100; i++) {
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reg = inb(priv->ioaddr + RTL_REG_CHIPCMD);
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if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
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break;
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udelay(100);
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}
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}
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static void rtl8139_reset(struct rtl8139_priv *priv)
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{
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int i;
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priv->cur_rx = 0;
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priv->cur_tx = 0;
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rtl8139_hw_reset(priv);
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for (i = 0; i < ETH_ALEN; i++)
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outb(priv->enetaddr[i], priv->ioaddr + RTL_REG_MAC0 + i);
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/* Must enable Tx/Rx before setting transfer thresholds! */
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outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
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priv->ioaddr + RTL_REG_CHIPCMD);
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/* accept no frames yet! */
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outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
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outl((TX_DMA_BURST << 8) | 0x03000000, priv->ioaddr + RTL_REG_TXCONFIG);
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/*
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* The Linux driver changes RTL_REG_CONFIG1 here to use a different
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* LED pattern for half duplex or full/autodetect duplex (for
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* full/autodetect, the outputs are TX/RX, Link10/100, FULL, while
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* for half duplex it uses TX/RX, Link100, Link10). This is messy,
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* because it doesn't match the inscription on the mounting bracket.
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* It should not be changed from the configuration EEPROM default,
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* because the card manufacturer should have set that to match the
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* card.
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*/
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debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
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flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
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outl(phys_to_bus(priv->devno, (int)rx_ring), priv->ioaddr + RTL_REG_RXBUF);
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/*
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* If we add multicast support, the RTL_REG_MAR0 register would have
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* to be initialized to 0xffffffffffffffff (two 32 bit accesses).
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* Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and
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* unicast.
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*/
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outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
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priv->ioaddr + RTL_REG_CHIPCMD);
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outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
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/* Start the chip's Tx and Rx process. */
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outl(0, priv->ioaddr + RTL_REG_RXMISSED);
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rtl8139_set_rx_mode(priv);
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/* Disable all known interrupts by setting the interrupt mask. */
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outw(0, priv->ioaddr + RTL_REG_INTRMASK);
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}
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static int rtl8139_send_common(struct rtl8139_priv *priv,
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void *packet, int length)
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{
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unsigned int len = length;
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unsigned long txstatus;
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unsigned int status;
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int i = 0;
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memcpy(tx_buffer, packet, length);
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debug_cond(DEBUG_TX, "sending %d bytes\n", len);
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/*
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* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
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* bytes are sent automatically for the FCS, totalling to 64 bytes).
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*/
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while (len < ETH_ZLEN)
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tx_buffer[len++] = '\0';
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flush_cache((unsigned long)tx_buffer, length);
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outl(phys_to_bus(priv->devno, (unsigned long)tx_buffer),
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priv->ioaddr + RTL_REG_TXADDR0 + priv->cur_tx * 4);
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outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
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priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
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do {
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status = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
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/*
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* Only acknlowledge interrupt sources we can properly
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* handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
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* RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
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* rtl8139_recv() function.
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*/
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status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
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RTL_REG_INTRSTATUS_PCIERR;
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outw(status, priv->ioaddr + RTL_REG_INTRSTATUS);
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if (status)
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break;
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udelay(10);
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} while (i++ < RTL_TIMEOUT);
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txstatus = inl(priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
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if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
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debug_cond(DEBUG_TX,
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"tx timeout/error (%d usecs), status %hX txstatus %lX\n",
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10 * i, status, txstatus);
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rtl8139_reset(priv);
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return 0;
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}
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priv->cur_tx = (priv->cur_tx + 1) % NUM_TX_DESC;
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debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
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status, txstatus);
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return length;
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}
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static int rtl8139_recv_common(struct rtl8139_priv *priv, unsigned char *rxdata,
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uchar **packetp)
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{
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const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
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RTL_REG_INTRSTATUS_RXOVERFLOW |
|
|
RTL_REG_INTRSTATUS_RXOK;
|
|
unsigned int rx_size, rx_status;
|
|
unsigned int ring_offs;
|
|
int length = 0;
|
|
|
|
if (inb(priv->ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
|
|
return 0;
|
|
|
|
priv->rxstatus = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
|
|
/* See below for the rest of the interrupt acknowledges. */
|
|
outw(priv->rxstatus & ~rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
|
|
|
|
debug_cond(DEBUG_RX, "%s: int %hX ", __func__, priv->rxstatus);
|
|
|
|
ring_offs = priv->cur_rx % RX_BUF_LEN;
|
|
/* ring_offs is guaranteed being 4-byte aligned */
|
|
rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
|
|
rx_size = rx_status >> 16;
|
|
rx_status &= 0xffff;
|
|
|
|
if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
|
|
RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
|
|
RTL_STS_RXBADALIGN)) ||
|
|
(rx_size < ETH_ZLEN) ||
|
|
(rx_size > ETH_FRAME_LEN + 4)) {
|
|
printf("rx error %hX\n", rx_status);
|
|
/* this clears all interrupts still pending */
|
|
rtl8139_reset(priv);
|
|
return 0;
|
|
}
|
|
|
|
/* Received a good packet */
|
|
length = rx_size - 4; /* no one cares about the FCS */
|
|
if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
|
|
int semi_count = RX_BUF_LEN - ring_offs - 4;
|
|
|
|
memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
|
|
memcpy(&rxdata[semi_count], rx_ring,
|
|
rx_size - 4 - semi_count);
|
|
|
|
*packetp = rxdata;
|
|
debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
|
|
semi_count, rx_size - 4 - semi_count);
|
|
} else {
|
|
*packetp = rx_ring + ring_offs + 4;
|
|
debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
|
|
}
|
|
|
|
return length;
|
|
}
|
|
|
|
static int rtl8139_free_pkt_common(struct rtl8139_priv *priv, unsigned int len)
|
|
{
|
|
const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
|
|
RTL_REG_INTRSTATUS_RXOVERFLOW |
|
|
RTL_REG_INTRSTATUS_RXOK;
|
|
unsigned int rx_size = len + 4;
|
|
|
|
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
|
|
|
|
priv->cur_rx = ROUND(priv->cur_rx + rx_size + 4, 4);
|
|
outw(priv->cur_rx - 16, priv->ioaddr + RTL_REG_RXBUFPTR);
|
|
/*
|
|
* See RTL8139 Programming Guide V0.1 for the official handling of
|
|
* Rx overflow situations. The document itself contains basically
|
|
* no usable information, except for a few exception handling rules.
|
|
*/
|
|
outw(priv->rxstatus & rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rtl8139_init_common(struct rtl8139_priv *priv)
|
|
{
|
|
u8 reg;
|
|
|
|
/* Bring the chip out of low-power mode. */
|
|
outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
|
|
|
|
rtl8139_reset(priv);
|
|
|
|
reg = inb(priv->ioaddr + RTL_REG_MEDIASTATUS);
|
|
if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
|
|
printf("Cable not connected or other link failure\n");
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rtl8139_stop_common(struct rtl8139_priv *priv)
|
|
{
|
|
rtl8139_hw_reset(priv);
|
|
}
|
|
|
|
static void rtl8139_get_hwaddr(struct rtl8139_priv *priv)
|
|
{
|
|
unsigned short *ap = (unsigned short *)priv->enetaddr;
|
|
int i, addr_len;
|
|
|
|
/* Bring the chip out of low-power mode. */
|
|
outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
|
|
|
|
addr_len = rtl8139_read_eeprom(priv, 0, 8) == 0x8129 ? 8 : 6;
|
|
for (i = 0; i < 3; i++)
|
|
*ap++ = le16_to_cpu(rtl8139_read_eeprom(priv, i + 7, addr_len));
|
|
}
|
|
|
|
static void rtl8139_name(char *str, int card_number)
|
|
{
|
|
sprintf(str, "RTL8139#%u", card_number);
|
|
}
|
|
|
|
static struct pci_device_id supported[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139) },
|
|
{ }
|
|
};
|
|
|
|
static int rtl8139_start(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *plat = dev_get_plat(dev);
|
|
struct rtl8139_priv *priv = dev_get_priv(dev);
|
|
|
|
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
|
|
|
|
return rtl8139_init_common(priv);
|
|
}
|
|
|
|
static void rtl8139_stop(struct udevice *dev)
|
|
{
|
|
struct rtl8139_priv *priv = dev_get_priv(dev);
|
|
|
|
rtl8139_stop_common(priv);
|
|
}
|
|
|
|
static int rtl8139_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct rtl8139_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = rtl8139_send_common(priv, packet, length);
|
|
|
|
return ret ? 0 : -ETIMEDOUT;
|
|
}
|
|
|
|
static int rtl8139_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct rtl8139_priv *priv = dev_get_priv(dev);
|
|
static unsigned char rxdata[RX_BUF_LEN];
|
|
|
|
return rtl8139_recv_common(priv, rxdata, packetp);
|
|
}
|
|
|
|
static int rtl8139_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
{
|
|
struct rtl8139_priv *priv = dev_get_priv(dev);
|
|
|
|
rtl8139_free_pkt_common(priv, length);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rtl8139_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *plat = dev_get_plat(dev);
|
|
struct rtl8139_priv *priv = dev_get_priv(dev);
|
|
|
|
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
|
|
|
|
rtl8139_reset(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rtl8139_read_rom_hwaddr(struct udevice *dev)
|
|
{
|
|
struct rtl8139_priv *priv = dev_get_priv(dev);
|
|
|
|
rtl8139_get_hwaddr(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rtl8139_bind(struct udevice *dev)
|
|
{
|
|
static int card_number;
|
|
char name[16];
|
|
|
|
rtl8139_name(name, card_number++);
|
|
|
|
return device_set_name(dev, name);
|
|
}
|
|
|
|
static int rtl8139_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *plat = dev_get_plat(dev);
|
|
struct rtl8139_priv *priv = dev_get_priv(dev);
|
|
u32 iobase;
|
|
|
|
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
|
|
iobase &= ~0xf;
|
|
|
|
debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
|
|
|
|
priv->devno = dev;
|
|
priv->ioaddr = (unsigned long)bus_to_phys(dev, iobase);
|
|
|
|
rtl8139_get_hwaddr(priv);
|
|
memcpy(plat->enetaddr, priv->enetaddr, sizeof(priv->enetaddr));
|
|
|
|
dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops rtl8139_ops = {
|
|
.start = rtl8139_start,
|
|
.send = rtl8139_send,
|
|
.recv = rtl8139_recv,
|
|
.stop = rtl8139_stop,
|
|
.free_pkt = rtl8139_free_pkt,
|
|
.write_hwaddr = rtl8139_write_hwaddr,
|
|
.read_rom_hwaddr = rtl8139_read_rom_hwaddr,
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_rtl8139) = {
|
|
.name = "eth_rtl8139",
|
|
.id = UCLASS_ETH,
|
|
.bind = rtl8139_bind,
|
|
.probe = rtl8139_probe,
|
|
.ops = &rtl8139_ops,
|
|
.priv_auto = sizeof(struct rtl8139_priv),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
};
|
|
|
|
U_BOOT_PCI_DEVICE(eth_rtl8139, supported);
|