mirror of
https://github.com/AsahiLinux/u-boot
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ffb0f6f488
Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
605 lines
15 KiB
C
605 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <errno.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include <console.h>
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#include <time.h>
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#include <wait_bit.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <linux/delay.h>
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#include <linux/mii.h>
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#include "pic32_eth.h"
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#define MAX_RX_BUF_SIZE 1536
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#define MAX_RX_DESCR PKTBUFSRX
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#define MAX_TX_DESCR 2
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DECLARE_GLOBAL_DATA_PTR;
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struct pic32eth_dev {
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struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
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struct eth_dma_desc txd_ring[MAX_TX_DESCR];
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u32 rxd_idx; /* index of RX desc to read */
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/* regs */
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struct pic32_ectl_regs *ectl_regs;
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struct pic32_emac_regs *emac_regs;
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/* Phy */
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struct phy_device *phydev;
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phy_interface_t phyif;
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u32 phy_addr;
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struct gpio_desc rst_gpio;
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};
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void __weak board_netphy_reset(void *dev)
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{
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struct pic32eth_dev *priv = dev;
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if (!dm_gpio_is_valid(&priv->rst_gpio))
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return;
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/* phy reset */
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dm_gpio_set_value(&priv->rst_gpio, 0);
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udelay(300);
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dm_gpio_set_value(&priv->rst_gpio, 1);
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udelay(300);
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}
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/* Initialize mii(MDIO) interface, discover which PHY is
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* attached to the device, and configure it properly.
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*/
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static int pic32_mii_init(struct pic32eth_dev *priv)
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{
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struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
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struct pic32_emac_regs *emac_p = priv->emac_regs;
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/* board phy reset */
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board_netphy_reset(priv);
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/* disable RX, TX & all transactions */
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writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
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/* wait till busy */
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wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
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CONFIG_SYS_HZ, false);
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/* turn controller ON to access PHY over MII */
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writel(ETHCON_ON, &ectl_p->con1.set);
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mdelay(10);
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/* reset MAC */
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writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */
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mdelay(10);
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writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */
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/* initialize MDIO/MII */
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if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
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writel(EMAC_RMII_RESET, &emac_p->supp.set);
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mdelay(10);
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writel(EMAC_RMII_RESET, &emac_p->supp.clr);
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}
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return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii);
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}
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static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
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{
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struct mii_dev *mii;
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mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
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/* find & connect PHY */
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priv->phydev = phy_connect(mii, priv->phy_addr,
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dev, priv->phyif);
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if (!priv->phydev) {
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printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
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return 0;
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}
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/* Wait for phy to complete reset */
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mdelay(10);
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/* configure supported modes */
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priv->phydev->supported = SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_Autoneg;
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priv->phydev->advertising = ADVERTISED_10baseT_Half |
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ADVERTISED_10baseT_Full |
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ADVERTISED_100baseT_Half |
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ADVERTISED_100baseT_Full |
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ADVERTISED_Autoneg;
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priv->phydev->autoneg = AUTONEG_ENABLE;
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return 0;
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}
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/* Configure MAC based on negotiated speed and duplex
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* reported by PHY.
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*/
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static int pic32_mac_adjust_link(struct pic32eth_dev *priv)
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{
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struct phy_device *phydev = priv->phydev;
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struct pic32_emac_regs *emac_p = priv->emac_regs;
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return -EINVAL;
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}
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if (phydev->duplex) {
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writel(EMAC_FULLDUP, &emac_p->cfg2.set);
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writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw);
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} else {
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writel(EMAC_FULLDUP, &emac_p->cfg2.clr);
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writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
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}
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switch (phydev->speed) {
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case SPEED_100:
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writel(EMAC_RMII_SPD100, &emac_p->supp.set);
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break;
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case SPEED_10:
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writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
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break;
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default:
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printf("%s: Speed was bad\n", phydev->dev->name);
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return -EINVAL;
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}
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printf("pic32eth: PHY is %s with %dbase%s, %s\n",
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phydev->drv->name, phydev->speed,
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(phydev->port == PORT_TP) ? "T" : "X",
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(phydev->duplex) ? "full" : "half");
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return 0;
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}
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static void pic32_mac_init(struct pic32eth_dev *priv, u8 *macaddr)
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{
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struct pic32_emac_regs *emac_p = priv->emac_regs;
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u32 stat = 0, v;
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u64 expire;
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v = EMAC_TXPAUSE | EMAC_RXPAUSE | EMAC_RXENABLE;
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writel(v, &emac_p->cfg1.raw);
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v = EMAC_EXCESS | EMAC_AUTOPAD | EMAC_PADENABLE |
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EMAC_CRCENABLE | EMAC_LENGTHCK | EMAC_FULLDUP;
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writel(v, &emac_p->cfg2.raw);
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/* recommended back-to-back inter-packet gap for 10 Mbps half duplex */
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writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
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/* recommended non-back-to-back interpacket gap is 0xc12 */
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writel(0xc12, &emac_p->ipgr.raw);
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/* recommended collision window retry limit is 0x370F */
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writel(0x370f, &emac_p->clrt.raw);
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/* set maximum frame length: allow VLAN tagged frame */
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writel(0x600, &emac_p->maxf.raw);
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/* set the mac address */
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writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw);
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writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw);
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writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw);
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/* default, enable 10 Mbps operation */
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writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
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/* wait until link status UP or deadline elapsed */
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expire = get_ticks() + get_tbclk() * 2;
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for (; get_ticks() < expire;) {
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stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR);
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if (stat & BMSR_LSTATUS)
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break;
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}
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if (!(stat & BMSR_LSTATUS))
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printf("MAC: Link is DOWN!\n");
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/* delay to stabilize before any tx/rx */
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mdelay(10);
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}
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static void pic32_mac_reset(struct pic32eth_dev *priv)
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{
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struct pic32_emac_regs *emac_p = priv->emac_regs;
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struct mii_dev *mii;
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/* Reset MAC */
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writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
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mdelay(10);
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/* clear reset */
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writel(0, &emac_p->cfg1.raw);
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/* Reset MII */
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mii = priv->phydev->bus;
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if (mii && mii->reset)
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mii->reset(mii);
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}
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/* initializes the MAC and PHY, then establishes a link */
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static void pic32_ctrl_reset(struct pic32eth_dev *priv)
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{
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struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
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u32 v;
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/* disable RX, TX & any other transactions */
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writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
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/* wait till busy */
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wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
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CONFIG_SYS_HZ, false);
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/* decrement received buffcnt to zero. */
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while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
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writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
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/* clear any existing interrupt event */
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writel(0xffffffff, &ectl_p->irq.clr);
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/* clear RX/TX start address */
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writel(0xffffffff, &ectl_p->txst.clr);
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writel(0xffffffff, &ectl_p->rxst.clr);
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/* clear the receive filters */
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writel(0x00ff, &ectl_p->rxfc.clr);
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/* set the receive filters
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* ETH_FILT_CRC_ERR_REJECT
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* ETH_FILT_RUNT_REJECT
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* ETH_FILT_UCAST_ACCEPT
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* ETH_FILT_MCAST_ACCEPT
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* ETH_FILT_BCAST_ACCEPT
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*/
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v = ETHRXFC_BCEN | ETHRXFC_MCEN | ETHRXFC_UCEN |
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ETHRXFC_RUNTEN | ETHRXFC_CRCOKEN;
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writel(v, &ectl_p->rxfc.set);
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/* turn controller ON to access PHY over MII */
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writel(ETHCON_ON, &ectl_p->con1.set);
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}
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static void pic32_rx_desc_init(struct pic32eth_dev *priv)
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{
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struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
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struct eth_dma_desc *rxd;
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u32 idx, bufsz;
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priv->rxd_idx = 0;
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for (idx = 0; idx < MAX_RX_DESCR; idx++) {
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rxd = &priv->rxd_ring[idx];
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/* hw owned */
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rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY;
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/* packet buffer address */
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rxd->data_buff = virt_to_phys(net_rx_packets[idx]);
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/* link to next desc */
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rxd->next_ed = virt_to_phys(rxd + 1);
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/* reset status */
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rxd->stat1 = 0;
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rxd->stat2 = 0;
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/* decrement bufcnt */
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writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
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}
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/* link last descr to beginning of list */
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rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]);
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/* flush rx ring */
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flush_dcache_range((ulong)priv->rxd_ring,
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(ulong)priv->rxd_ring + sizeof(priv->rxd_ring));
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/* set rx desc-ring start address */
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writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw);
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/* RX Buffer size */
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bufsz = readl(&ectl_p->con2.raw);
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bufsz &= ~(ETHCON_RXBUFSZ << ETHCON_RXBUFSZ_SHFT);
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bufsz |= ((MAX_RX_BUF_SIZE / 16) << ETHCON_RXBUFSZ_SHFT);
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writel(bufsz, &ectl_p->con2.raw);
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/* enable the receiver in hardware which allows hardware
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* to DMA received pkts to the descriptor pointer address.
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*/
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writel(ETHCON_RXEN, &ectl_p->con1.set);
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}
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static int pic32_eth_start(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct pic32eth_dev *priv = dev_get_priv(dev);
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/* controller */
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pic32_ctrl_reset(priv);
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/* reset MAC */
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pic32_mac_reset(priv);
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/* configure PHY */
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phy_config(priv->phydev);
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/* initialize MAC */
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pic32_mac_init(priv, &pdata->enetaddr[0]);
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/* init RX descriptor; TX descriptors are handled in xmit */
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pic32_rx_desc_init(priv);
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/* Start up & update link status of PHY */
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phy_startup(priv->phydev);
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/* adjust mac with phy link status */
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return pic32_mac_adjust_link(priv);
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}
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static void pic32_eth_stop(struct udevice *dev)
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{
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struct pic32eth_dev *priv = dev_get_priv(dev);
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struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
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struct pic32_emac_regs *emac_p = priv->emac_regs;
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/* Reset the phy if the controller is enabled */
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if (readl(&ectl_p->con1.raw) & ETHCON_ON)
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phy_reset(priv->phydev);
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/* Shut down the PHY */
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phy_shutdown(priv->phydev);
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/* Stop rx/tx */
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writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
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mdelay(10);
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/* reset MAC */
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writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
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/* clear reset */
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writel(0, &emac_p->cfg1.raw);
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mdelay(10);
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/* disable controller */
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writel(ETHCON_ON, &ectl_p->con1.clr);
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mdelay(10);
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/* wait until everything is down */
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wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
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2 * CONFIG_SYS_HZ, false);
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/* clear any existing interrupt event */
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writel(0xffffffff, &ectl_p->irq.clr);
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}
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static int pic32_eth_send(struct udevice *dev, void *packet, int length)
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{
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struct pic32eth_dev *priv = dev_get_priv(dev);
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struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
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struct eth_dma_desc *txd;
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u64 deadline;
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txd = &priv->txd_ring[0];
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/* set proper flags & length in descriptor header */
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txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length);
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/* pass buffer address to hardware */
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txd->data_buff = virt_to_phys(packet);
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debug("%s: %d / .hdr %x, .data_buff %x, .stat %x, .nexted %x\n",
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__func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2,
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txd->next_ed);
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/* cache flush (packet) */
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flush_dcache_range((ulong)packet, (ulong)packet + length);
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/* cache flush (txd) */
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flush_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
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/* pass descriptor table base to h/w */
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writel(virt_to_phys(txd), &ectl_p->txst.raw);
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/* ready to send enabled, hardware can now send the packet(s) */
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writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set);
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/* wait until tx has completed and h/w has released ownership
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* of the tx descriptor or timeout elapsed.
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*/
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deadline = get_ticks() + get_tbclk();
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for (;;) {
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/* check timeout */
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if (get_ticks() > deadline)
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return -ETIMEDOUT;
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if (ctrlc())
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return -EINTR;
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/* tx completed ? */
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if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) {
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udelay(1);
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continue;
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}
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/* h/w not released ownership yet? */
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invalidate_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
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if (!(txd->hdr & EDH_EOWN))
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break;
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}
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return 0;
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}
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static int pic32_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct pic32eth_dev *priv = dev_get_priv(dev);
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struct eth_dma_desc *rxd;
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u32 idx = priv->rxd_idx;
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u32 rx_count;
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/* find the next ready to receive */
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rxd = &priv->rxd_ring[idx];
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invalidate_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
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/* check if owned by MAC */
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if (rxd->hdr & EDH_EOWN)
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return -EAGAIN;
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/* Sanity check on header: SOP and EOP */
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if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) {
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printf("%s: %s, rx pkt across multiple descr\n",
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__FILE__, __func__);
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return 0;
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}
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debug("%s: %d /idx %i, hdr=%x, data_buff %x, stat %x, nexted %x\n",
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__func__, __LINE__, idx, rxd->hdr,
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rxd->data_buff, rxd->stat2, rxd->next_ed);
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/* Sanity check on rx_stat: OK, CRC */
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if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) {
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debug("%s: %s: Error, rx problem detected\n",
|
|
__FILE__, __func__);
|
|
return 0;
|
|
}
|
|
|
|
/* invalidate dcache */
|
|
rx_count = RSV_RX_COUNT(rxd->stat2);
|
|
invalidate_dcache_range((ulong)net_rx_packets[idx],
|
|
(ulong)net_rx_packets[idx] + rx_count);
|
|
|
|
/* Pass the packet to protocol layer */
|
|
*packetp = net_rx_packets[idx];
|
|
|
|
/* increment number of bytes rcvd (ignore CRC) */
|
|
return rx_count - 4;
|
|
}
|
|
|
|
static int pic32_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
{
|
|
struct pic32eth_dev *priv = dev_get_priv(dev);
|
|
struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
|
|
struct eth_dma_desc *rxd;
|
|
int idx = priv->rxd_idx;
|
|
|
|
/* sanity check */
|
|
if (packet != net_rx_packets[idx]) {
|
|
printf("rxd_id %d: packet is not matched,\n", idx);
|
|
return -EAGAIN;
|
|
}
|
|
|
|
/* prepare for receive */
|
|
rxd = &priv->rxd_ring[idx];
|
|
rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN;
|
|
|
|
flush_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
|
|
|
|
/* decrement rx pkt count */
|
|
writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
|
|
|
|
debug("%s: %d / idx %i, hdr %x, data_buff %x, stat %x, nexted %x\n",
|
|
__func__, __LINE__, idx, rxd->hdr, rxd->data_buff,
|
|
rxd->stat2, rxd->next_ed);
|
|
|
|
priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops pic32_eth_ops = {
|
|
.start = pic32_eth_start,
|
|
.send = pic32_eth_send,
|
|
.recv = pic32_eth_recv,
|
|
.free_pkt = pic32_eth_free_pkt,
|
|
.stop = pic32_eth_stop,
|
|
};
|
|
|
|
static int pic32_eth_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct pic32eth_dev *priv = dev_get_priv(dev);
|
|
void __iomem *iobase;
|
|
fdt_addr_t addr;
|
|
fdt_size_t size;
|
|
int offset = 0;
|
|
int phy_addr = -1;
|
|
|
|
addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
|
|
&size);
|
|
if (addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
iobase = ioremap(addr, size);
|
|
pdata->iobase = (phys_addr_t)addr;
|
|
|
|
/* get phy mode */
|
|
pdata->phy_interface = dev_read_phy_mode(dev);
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
|
|
return -EINVAL;
|
|
|
|
/* get phy addr */
|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
|
|
"phy-handle");
|
|
if (offset > 0)
|
|
phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
|
|
|
|
/* phy reset gpio */
|
|
gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
|
|
&priv->rst_gpio, GPIOD_IS_OUT);
|
|
|
|
priv->phyif = pdata->phy_interface;
|
|
priv->phy_addr = phy_addr;
|
|
priv->ectl_regs = iobase;
|
|
priv->emac_regs = iobase + PIC32_EMAC1CFG1;
|
|
|
|
pic32_mii_init(priv);
|
|
|
|
return pic32_phy_init(priv, dev);
|
|
}
|
|
|
|
static int pic32_eth_remove(struct udevice *dev)
|
|
{
|
|
struct pic32eth_dev *priv = dev_get_priv(dev);
|
|
struct mii_dev *bus;
|
|
|
|
dm_gpio_free(dev, &priv->rst_gpio);
|
|
phy_shutdown(priv->phydev);
|
|
free(priv->phydev);
|
|
bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
|
|
mdio_unregister(bus);
|
|
mdio_free(bus);
|
|
iounmap(priv->ectl_regs);
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id pic32_eth_ids[] = {
|
|
{ .compatible = "microchip,pic32mzda-eth" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pic32_ethernet) = {
|
|
.name = "pic32_ethernet",
|
|
.id = UCLASS_ETH,
|
|
.of_match = pic32_eth_ids,
|
|
.probe = pic32_eth_probe,
|
|
.remove = pic32_eth_remove,
|
|
.ops = &pic32_eth_ops,
|
|
.priv_auto = sizeof(struct pic32eth_dev),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
};
|