mirror of
https://github.com/AsahiLinux/u-boot
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32dc677276
As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini <trini@konsulko.com>
562 lines
13 KiB
C
562 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
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*
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* This driver for AMD PCnet network controllers is derived from the
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* Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <linux/delay.h>
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#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
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#define PCNET_DEBUG1(fmt,args...) \
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debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
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#define PCNET_DEBUG2(fmt,args...) \
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debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
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/*
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* Set the number of Tx and Rx buffers, using Log_2(# buffers).
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* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
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* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
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*/
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#define PCNET_LOG_TX_BUFFERS 0
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#define PCNET_LOG_RX_BUFFERS 2
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#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
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#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
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#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
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#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
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#define PKT_BUF_SZ 1544
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/* The PCNET Rx and Tx ring descriptors. */
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struct pcnet_rx_head {
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u32 base;
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s16 buf_length;
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s16 status;
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u32 msg_length;
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u32 reserved;
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};
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struct pcnet_tx_head {
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u32 base;
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s16 length;
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s16 status;
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u32 misc;
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u32 reserved;
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};
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/* The PCNET 32-Bit initialization block, described in databook. */
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struct pcnet_init_block {
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u16 mode;
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u16 tlen_rlen;
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u8 phys_addr[6];
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u16 reserved;
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u32 filter[2];
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/* Receive and transmit ring base, along with extra bits. */
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u32 rx_ring;
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u32 tx_ring;
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u32 reserved2;
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};
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struct pcnet_uncached_priv {
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struct pcnet_rx_head rx_ring[RX_RING_SIZE];
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struct pcnet_tx_head tx_ring[TX_RING_SIZE];
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struct pcnet_init_block init_block;
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} __aligned(ARCH_DMA_MINALIGN);
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struct pcnet_priv {
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struct pcnet_uncached_priv ucp;
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/* Receive Buffer space */
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unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
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struct pcnet_uncached_priv *uc;
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struct udevice *dev;
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const char *name;
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void __iomem *iobase;
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u8 *enetaddr;
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u16 status;
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int cur_rx;
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int cur_tx;
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};
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/* Offsets from base I/O address for WIO mode */
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#define PCNET_RDP 0x10
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#define PCNET_RAP 0x12
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#define PCNET_RESET 0x14
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#define PCNET_BDP 0x16
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static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
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{
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writew(index, lp->iobase + PCNET_RAP);
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return readw(lp->iobase + PCNET_RDP);
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}
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static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
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{
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writew(index, lp->iobase + PCNET_RAP);
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writew(val, lp->iobase + PCNET_RDP);
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}
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static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
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{
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writew(index, lp->iobase + PCNET_RAP);
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return readw(lp->iobase + PCNET_BDP);
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}
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static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
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{
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writew(index, lp->iobase + PCNET_RAP);
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writew(val, lp->iobase + PCNET_BDP);
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}
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static void pcnet_reset(struct pcnet_priv *lp)
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{
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readw(lp->iobase + PCNET_RESET);
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}
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static int pcnet_check(struct pcnet_priv *lp)
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{
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writew(88, lp->iobase + PCNET_RAP);
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return readw(lp->iobase + PCNET_RAP) == 88;
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}
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static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
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{
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void *virt_addr = addr;
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return dm_pci_virt_to_mem(lp->dev, virt_addr);
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}
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static struct pci_device_id supported[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
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{}
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};
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static int pcnet_probe_common(struct pcnet_priv *lp)
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{
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int chip_version;
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char *chipname;
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int i;
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/* Reset the PCnet controller */
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pcnet_reset(lp);
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/* Check if register access is working */
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if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
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printf("%s: CSR register access check failed\n", lp->name);
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return -1;
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}
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/* Identify the chip */
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chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
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if ((chip_version & 0xfff) != 0x003)
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return -1;
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chip_version = (chip_version >> 12) & 0xffff;
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switch (chip_version) {
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case 0x2621:
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chipname = "PCnet/PCI II 79C970A"; /* PCI */
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break;
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case 0x2625:
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chipname = "PCnet/FAST III 79C973"; /* PCI */
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break;
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case 0x2627:
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chipname = "PCnet/FAST III 79C975"; /* PCI */
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break;
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default:
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printf("%s: PCnet version %#x not supported\n",
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lp->name, chip_version);
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return -1;
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}
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PCNET_DEBUG1("AMD %s\n", chipname);
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/*
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* In most chips, after a chip reset, the ethernet address is read from
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* the station address PROM at the base address and programmed into the
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* "Physical Address Registers" CSR12-14.
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*/
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for (i = 0; i < 3; i++) {
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unsigned int val;
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val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
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/* There may be endianness issues here. */
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lp->enetaddr[2 * i] = val & 0x0ff;
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lp->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
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}
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return 0;
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}
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static int pcnet_init_common(struct pcnet_priv *lp)
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{
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struct pcnet_uncached_priv *uc;
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int i, val;
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unsigned long addr;
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PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
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/* Switch pcnet to 32bit mode */
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pcnet_write_bcr(lp, 20, 2);
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/* Set/reset autoselect bit */
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val = pcnet_read_bcr(lp, 2) & ~2;
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val |= 2;
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pcnet_write_bcr(lp, 2, val);
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/* Enable auto negotiate, setup, disable fd */
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val = pcnet_read_bcr(lp, 32) & ~0x98;
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val |= 0x20;
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pcnet_write_bcr(lp, 32, val);
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/*
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* Enable NOUFLO on supported controllers, with the transmit
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* start point set to the full packet. This will cause entire
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* packets to be buffered by the ethernet controller before
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* transmission, eliminating underflows which are common on
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* slower devices. Controllers which do not support NOUFLO will
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* simply be left with a larger transmit FIFO threshold.
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*/
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val = pcnet_read_bcr(lp, 18);
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val |= 1 << 11;
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pcnet_write_bcr(lp, 18, val);
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val = pcnet_read_csr(lp, 80);
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val |= 0x3 << 10;
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pcnet_write_csr(lp, 80, val);
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uc = lp->uc;
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uc->init_block.mode = cpu_to_le16(0x0000);
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uc->init_block.filter[0] = 0x00000000;
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uc->init_block.filter[1] = 0x00000000;
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/*
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* Initialize the Rx ring.
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*/
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lp->cur_rx = 0;
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for (i = 0; i < RX_RING_SIZE; i++) {
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addr = pcnet_virt_to_mem(lp, lp->rx_buf[i]);
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uc->rx_ring[i].base = cpu_to_le32(addr);
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uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
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uc->rx_ring[i].status = cpu_to_le16(0x8000);
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PCNET_DEBUG1
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("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
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uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
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uc->rx_ring[i].status);
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}
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/*
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* Initialize the Tx ring. The Tx buffer address is filled in as
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* needed, but we do need to clear the upper ownership bit.
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*/
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lp->cur_tx = 0;
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for (i = 0; i < TX_RING_SIZE; i++) {
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uc->tx_ring[i].base = 0;
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uc->tx_ring[i].status = 0;
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}
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/*
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* Setup Init Block.
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*/
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PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
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for (i = 0; i < 6; i++) {
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lp->uc->init_block.phys_addr[i] = lp->enetaddr[i];
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PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
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}
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uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
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RX_RING_LEN_BITS);
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addr = pcnet_virt_to_mem(lp, uc->rx_ring);
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uc->init_block.rx_ring = cpu_to_le32(addr);
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addr = pcnet_virt_to_mem(lp, uc->tx_ring);
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uc->init_block.tx_ring = cpu_to_le32(addr);
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PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
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uc->init_block.tlen_rlen,
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uc->init_block.rx_ring, uc->init_block.tx_ring);
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/*
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* Tell the controller where the Init Block is located.
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*/
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barrier();
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addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
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pcnet_write_csr(lp, 1, addr & 0xffff);
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pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
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pcnet_write_csr(lp, 4, 0x0915);
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pcnet_write_csr(lp, 0, 0x0001); /* start */
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/* Wait for Init Done bit */
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for (i = 10000; i > 0; i--) {
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if (pcnet_read_csr(lp, 0) & 0x0100)
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break;
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udelay(10);
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}
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if (i <= 0) {
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printf("%s: TIMEOUT: controller init failed\n", lp->name);
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pcnet_reset(lp);
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return -1;
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}
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/*
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* Finally start network controller operation.
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*/
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pcnet_write_csr(lp, 0, 0x0002);
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return 0;
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}
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static int pcnet_send_common(struct pcnet_priv *lp, void *packet, int pkt_len)
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{
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int i, status;
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u32 addr;
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struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
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PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
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packet);
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flush_dcache_range((unsigned long)packet,
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(unsigned long)packet + pkt_len);
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/* Wait for completion by testing the OWN bit */
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for (i = 1000; i > 0; i--) {
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status = readw(&entry->status);
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if ((status & 0x8000) == 0)
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break;
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udelay(100);
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PCNET_DEBUG2(".");
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}
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if (i <= 0) {
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printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
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lp->name, lp->cur_tx, status);
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pkt_len = 0;
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goto failure;
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}
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/*
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* Setup Tx ring. Caution: the write order is important here,
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* set the status with the "ownership" bits last.
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*/
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addr = pcnet_virt_to_mem(lp, packet);
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writew(-pkt_len, &entry->length);
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writel(0, &entry->misc);
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writel(addr, &entry->base);
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writew(0x8300, &entry->status);
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/* Trigger an immediate send poll. */
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pcnet_write_csr(lp, 0, 0x0008);
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failure:
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if (++lp->cur_tx >= TX_RING_SIZE)
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lp->cur_tx = 0;
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PCNET_DEBUG2("done\n");
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return pkt_len;
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}
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static int pcnet_recv_common(struct pcnet_priv *lp, unsigned char **bufp)
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{
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struct pcnet_rx_head *entry;
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unsigned char *buf;
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int pkt_len = 0;
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u16 err_status;
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entry = &lp->uc->rx_ring[lp->cur_rx];
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/*
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* If we own the next entry, it's a new packet. Send it up.
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*/
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lp->status = readw(&entry->status);
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if ((lp->status & 0x8000) != 0)
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return 0;
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err_status = lp->status >> 8;
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if (err_status != 0x03) { /* There was an error. */
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printf("%s: Rx%d", lp->name, lp->cur_rx);
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PCNET_DEBUG1(" (status=0x%x)", err_status);
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if (err_status & 0x20)
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printf(" Frame");
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if (err_status & 0x10)
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printf(" Overflow");
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if (err_status & 0x08)
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printf(" CRC");
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if (err_status & 0x04)
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printf(" Fifo");
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printf(" Error\n");
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lp->status &= 0x03ff;
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return 0;
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}
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pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
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if (pkt_len < 60) {
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printf("%s: Rx%d: invalid packet length %d\n",
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lp->name, lp->cur_rx, pkt_len);
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return 0;
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}
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*bufp = lp->rx_buf[lp->cur_rx];
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invalidate_dcache_range((unsigned long)*bufp,
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(unsigned long)*bufp + pkt_len);
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PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
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lp->cur_rx, pkt_len, buf);
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return pkt_len;
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}
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static void pcnet_free_pkt_common(struct pcnet_priv *lp, unsigned int len)
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{
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struct pcnet_rx_head *entry;
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entry = &lp->uc->rx_ring[lp->cur_rx];
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lp->status |= 0x8000;
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writew(lp->status, &entry->status);
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if (++lp->cur_rx >= RX_RING_SIZE)
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lp->cur_rx = 0;
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}
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static void pcnet_halt_common(struct pcnet_priv *lp)
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{
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int i;
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PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
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/* Reset the PCnet controller */
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pcnet_reset(lp);
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/* Wait for Stop bit */
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for (i = 1000; i > 0; i--) {
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if (pcnet_read_csr(lp, 0) & 0x4)
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break;
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udelay(10);
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}
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if (i <= 0)
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printf("%s: TIMEOUT: controller reset failed\n", lp->name);
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}
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static int pcnet_start(struct udevice *dev)
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{
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struct eth_pdata *plat = dev_get_plat(dev);
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struct pcnet_priv *priv = dev_get_priv(dev);
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memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
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return pcnet_init_common(priv);
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}
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static void pcnet_stop(struct udevice *dev)
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{
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struct pcnet_priv *priv = dev_get_priv(dev);
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pcnet_halt_common(priv);
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}
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static int pcnet_send(struct udevice *dev, void *packet, int length)
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{
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struct pcnet_priv *priv = dev_get_priv(dev);
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int ret;
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ret = pcnet_send_common(priv, packet, length);
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return ret ? 0 : -ETIMEDOUT;
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}
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static int pcnet_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct pcnet_priv *priv = dev_get_priv(dev);
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return pcnet_recv_common(priv, packetp);
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}
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static int pcnet_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct pcnet_priv *priv = dev_get_priv(dev);
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pcnet_free_pkt_common(priv, length);
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return 0;
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}
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static int pcnet_bind(struct udevice *dev)
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{
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static int card_number;
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char name[16];
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sprintf(name, "pcnet#%u", card_number++);
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return device_set_name(dev, name);
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}
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static int pcnet_probe(struct udevice *dev)
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{
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struct eth_pdata *plat = dev_get_plat(dev);
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struct pcnet_priv *lp = dev_get_priv(dev);
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u16 command, status;
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u32 iobase;
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int ret;
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|
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dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
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iobase &= ~0xf;
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|
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lp->uc = map_physmem((phys_addr_t)&lp->ucp,
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sizeof(lp->ucp), MAP_NOCACHE);
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lp->dev = dev;
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lp->name = dev->name;
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lp->enetaddr = plat->enetaddr;
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lp->iobase = (void *)dm_pci_mem_to_phys(dev, iobase);
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|
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flush_dcache_range((unsigned long)lp,
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|
(unsigned long)lp + sizeof(*lp));
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|
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command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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dm_pci_write_config16(dev, PCI_COMMAND, command);
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dm_pci_read_config16(dev, PCI_COMMAND, &status);
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if ((status & command) != command) {
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|
printf("%s: Couldn't enable IO access or Bus Mastering\n",
|
|
lp->name);
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return -EINVAL;
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|
}
|
|
|
|
dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
|
|
|
|
ret = pcnet_probe_common(lp);
|
|
if (ret)
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|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops pcnet_ops = {
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|
.start = pcnet_start,
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|
.send = pcnet_send,
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|
.recv = pcnet_recv,
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|
.stop = pcnet_stop,
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|
.free_pkt = pcnet_free_pkt,
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_pcnet) = {
|
|
.name = "eth_pcnet",
|
|
.id = UCLASS_ETH,
|
|
.bind = pcnet_bind,
|
|
.probe = pcnet_probe,
|
|
.ops = &pcnet_ops,
|
|
.priv_auto = sizeof(struct pcnet_priv),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
|
|
U_BOOT_PCI_DEVICE(eth_pcnet, supported);
|