mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 11:00:15 +00:00
6e7df1d151
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
656 lines
16 KiB
C
656 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* MediaTek ethernet IP driver for U-Boot
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*
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* Copyright (C) 2018 Stefan Roese <sr@denx.de>
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*
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* This code is mostly based on the code extracted from this MediaTek
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* github repository:
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*
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* https://github.com/MediaTek-Labs/linkit-smart-uboot.git
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*
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* I was not able to find a specific license or other developers
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* copyrights here, so I can't add them here.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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/* Ethernet frame engine register */
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#define PDMA_RELATED 0x0800
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#define TX_BASE_PTR0 (PDMA_RELATED + 0x000)
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#define TX_MAX_CNT0 (PDMA_RELATED + 0x004)
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#define TX_CTX_IDX0 (PDMA_RELATED + 0x008)
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#define TX_DTX_IDX0 (PDMA_RELATED + 0x00c)
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#define RX_BASE_PTR0 (PDMA_RELATED + 0x100)
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#define RX_MAX_CNT0 (PDMA_RELATED + 0x104)
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#define RX_CALC_IDX0 (PDMA_RELATED + 0x108)
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#define PDMA_GLO_CFG (PDMA_RELATED + 0x204)
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#define PDMA_RST_IDX (PDMA_RELATED + 0x208)
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#define DLY_INT_CFG (PDMA_RELATED + 0x20c)
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#define SDM_RELATED 0x0c00
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#define SDM_MAC_ADRL (SDM_RELATED + 0x0c) /* MAC address LSB */
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#define SDM_MAC_ADRH (SDM_RELATED + 0x10) /* MAC Address MSB */
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#define RST_DTX_IDX0 BIT(0)
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#define RST_DRX_IDX0 BIT(16)
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#define TX_DMA_EN BIT(0)
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#define TX_DMA_BUSY BIT(1)
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#define RX_DMA_EN BIT(2)
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#define RX_DMA_BUSY BIT(3)
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#define TX_WB_DDONE BIT(6)
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/* Ethernet switch register */
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#define MT7628_SWITCH_FCT0 0x0008
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#define MT7628_SWITCH_PFC1 0x0014
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#define MT7628_SWITCH_PVIDC0 0x0040
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#define MT7628_SWITCH_PVIDC1 0x0044
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#define MT7628_SWITCH_PVIDC2 0x0048
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#define MT7628_SWITCH_PVIDC3 0x004c
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#define MT7628_SWITCH_VMSC0 0x0070
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#define MT7628_SWITCH_FPA 0x0084
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#define MT7628_SWITCH_SOCPC 0x008c
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#define MT7628_SWITCH_POC0 0x0090
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#define MT7628_SWITCH_POC2 0x0098
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#define MT7628_SWITCH_SGC 0x009c
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#define MT7628_SWITCH_PCR0 0x00c0
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#define PCR0_PHY_ADDR GENMASK(4, 0)
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#define PCR0_PHY_REG GENMASK(12, 8)
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#define PCR0_WT_PHY_CMD BIT(13)
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#define PCR0_RD_PHY_CMD BIT(14)
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#define PCR0_WT_DATA GENMASK(31, 16)
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#define MT7628_SWITCH_PCR1 0x00c4
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#define PCR1_WT_DONE BIT(0)
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#define PCR1_RD_RDY BIT(1)
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#define PCR1_RD_DATA GENMASK(31, 16)
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#define MT7628_SWITCH_FPA1 0x00c8
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#define MT7628_SWITCH_FCT2 0x00cc
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#define MT7628_SWITCH_SGC2 0x00e4
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#define MT7628_SWITCH_BMU_CTRL 0x0110
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/* rxd2 */
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#define RX_DMA_DONE BIT(31)
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#define RX_DMA_LSO BIT(30)
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#define RX_DMA_PLEN0 GENMASK(29, 16)
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#define RX_DMA_TAG BIT(15)
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struct fe_rx_dma {
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unsigned int rxd1;
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unsigned int rxd2;
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unsigned int rxd3;
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unsigned int rxd4;
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} __packed __aligned(4);
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#define TX_DMA_PLEN0 GENMASK(29, 16)
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#define TX_DMA_LS1 BIT(14)
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#define TX_DMA_LS0 BIT(30)
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#define TX_DMA_DONE BIT(31)
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#define TX_DMA_INS_VLAN_MT7621 BIT(16)
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#define TX_DMA_INS_VLAN BIT(7)
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#define TX_DMA_INS_PPPOE BIT(12)
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#define TX_DMA_PN GENMASK(26, 24)
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struct fe_tx_dma {
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unsigned int txd1;
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unsigned int txd2;
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unsigned int txd3;
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unsigned int txd4;
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} __packed __aligned(4);
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#define NUM_RX_DESC 256
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#define NUM_TX_DESC 4
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#define NUM_PHYS 5
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#define PADDING_LENGTH 60
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#define MTK_QDMA_PAGE_SIZE 2048
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#define CFG_MDIO_TIMEOUT 100
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#define CFG_DMA_STOP_TIMEOUT 100
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#define CFG_TX_DMA_TIMEOUT 100
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struct mt7628_eth_dev {
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void __iomem *base; /* frame engine base address */
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void __iomem *eth_sw_base; /* switch base address */
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struct mii_dev *bus;
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struct fe_tx_dma *tx_ring;
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struct fe_rx_dma *rx_ring;
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u8 *rx_buf[NUM_RX_DESC];
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/* Point to the next RXD DMA wants to use in RXD Ring0 */
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int rx_dma_idx;
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/* Point to the next TXD in TXD Ring0 CPU wants to use */
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int tx_dma_idx;
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struct reset_ctl rst_ephy;
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struct phy_device *phy;
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int wan_port;
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};
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static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length);
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static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set)
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{
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void __iomem *base = priv->eth_sw_base;
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int ret;
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ret = wait_for_bit_le32(base + MT7628_SWITCH_PCR1, mask, mask_set,
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CFG_MDIO_TIMEOUT, false);
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if (ret) {
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printf("MDIO operation timeout!\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int mii_mgr_read(struct mt7628_eth_dev *priv,
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u32 phy_addr, u32 phy_register, u32 *read_data)
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{
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void __iomem *base = priv->eth_sw_base;
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u32 status = 0;
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u32 ret;
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*read_data = 0xffff;
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/* Make sure previous read operation is complete */
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ret = mdio_wait_read(priv, PCR1_RD_RDY, false);
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if (ret)
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return ret;
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writel(PCR0_RD_PHY_CMD |
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FIELD_PREP(PCR0_PHY_REG, phy_register) |
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FIELD_PREP(PCR0_PHY_ADDR, phy_addr),
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base + MT7628_SWITCH_PCR0);
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/* Make sure previous read operation is complete */
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ret = mdio_wait_read(priv, PCR1_RD_RDY, true);
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if (ret)
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return ret;
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status = readl(base + MT7628_SWITCH_PCR1);
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*read_data = FIELD_GET(PCR1_RD_DATA, status);
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return 0;
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}
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static int mii_mgr_write(struct mt7628_eth_dev *priv,
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u32 phy_addr, u32 phy_register, u32 write_data)
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{
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void __iomem *base = priv->eth_sw_base;
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u32 data;
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int ret;
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/* Make sure previous write operation is complete */
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ret = mdio_wait_read(priv, PCR1_WT_DONE, false);
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if (ret)
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return ret;
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data = FIELD_PREP(PCR0_WT_DATA, write_data) |
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FIELD_PREP(PCR0_PHY_REG, phy_register) |
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FIELD_PREP(PCR0_PHY_ADDR, phy_addr) |
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PCR0_WT_PHY_CMD;
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writel(data, base + MT7628_SWITCH_PCR0);
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return mdio_wait_read(priv, PCR1_WT_DONE, true);
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}
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static int mt7628_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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u32 val;
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int ret;
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ret = mii_mgr_read(bus->priv, addr, reg, &val);
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if (ret)
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return ret;
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return val;
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}
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static int mt7628_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 value)
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{
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return mii_mgr_write(bus->priv, addr, reg, value);
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}
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static void mt7628_ephy_init(struct mt7628_eth_dev *priv)
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{
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int i;
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mii_mgr_write(priv, 0, 31, 0x2000); /* change G2 page */
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mii_mgr_write(priv, 0, 26, 0x0000);
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for (i = 0; i < 5; i++) {
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mii_mgr_write(priv, i, 31, 0x8000); /* change L0 page */
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mii_mgr_write(priv, i, 0, 0x3100);
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/* EEE disable */
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mii_mgr_write(priv, i, 30, 0xa000);
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mii_mgr_write(priv, i, 31, 0xa000); /* change L2 page */
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mii_mgr_write(priv, i, 16, 0x0606);
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mii_mgr_write(priv, i, 23, 0x0f0e);
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mii_mgr_write(priv, i, 24, 0x1610);
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mii_mgr_write(priv, i, 30, 0x1f15);
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mii_mgr_write(priv, i, 28, 0x6111);
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}
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/* 100Base AOI setting */
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mii_mgr_write(priv, 0, 31, 0x5000); /* change G5 page */
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mii_mgr_write(priv, 0, 19, 0x004a);
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mii_mgr_write(priv, 0, 20, 0x015a);
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mii_mgr_write(priv, 0, 21, 0x00ee);
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mii_mgr_write(priv, 0, 22, 0x0033);
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mii_mgr_write(priv, 0, 23, 0x020a);
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mii_mgr_write(priv, 0, 24, 0x0000);
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mii_mgr_write(priv, 0, 25, 0x024a);
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mii_mgr_write(priv, 0, 26, 0x035a);
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mii_mgr_write(priv, 0, 27, 0x02ee);
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mii_mgr_write(priv, 0, 28, 0x0233);
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mii_mgr_write(priv, 0, 29, 0x000a);
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mii_mgr_write(priv, 0, 30, 0x0000);
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/* Fix EPHY idle state abnormal behavior */
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mii_mgr_write(priv, 0, 31, 0x4000); /* change G4 page */
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mii_mgr_write(priv, 0, 29, 0x000d);
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mii_mgr_write(priv, 0, 30, 0x0500);
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}
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static void rt305x_esw_init(struct mt7628_eth_dev *priv)
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{
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void __iomem *base = priv->eth_sw_base;
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void __iomem *reg;
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u32 val = 0, pvid;
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int i;
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/*
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* FC_RLS_TH=200, FC_SET_TH=160
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* DROP_RLS=120, DROP_SET_TH=80
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*/
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writel(0xc8a07850, base + MT7628_SWITCH_FCT0);
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writel(0x00000000, base + MT7628_SWITCH_SGC2);
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writel(0x00405555, base + MT7628_SWITCH_PFC1);
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writel(0x00007f7f, base + MT7628_SWITCH_POC0);
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writel(0x00007f7f, base + MT7628_SWITCH_POC2); /* disable VLAN */
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writel(0x0002500c, base + MT7628_SWITCH_FCT2);
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/* hashing algorithm=XOR48, aging interval=300sec */
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writel(0x0008a301, base + MT7628_SWITCH_SGC);
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writel(0x02404040, base + MT7628_SWITCH_SOCPC);
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/* Ext PHY Addr=0x1f */
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writel(0x3f502b28, base + MT7628_SWITCH_FPA1);
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writel(0x00000000, base + MT7628_SWITCH_FPA);
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/* 1us cycle number=125 (FE's clock=125Mhz) */
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writel(0x7d000000, base + MT7628_SWITCH_BMU_CTRL);
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/* LAN/WAN partition, WAN port will be unusable in u-boot network */
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if (priv->wan_port >= 0 && priv->wan_port < 6) {
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for (i = 0; i < 8; i++) {
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pvid = i == priv->wan_port ? 2 : 1;
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reg = base + MT7628_SWITCH_PVIDC0 + (i / 2) * 4;
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if (i % 2 == 0) {
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val = pvid;
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} else {
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val |= (pvid << 12);
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writel(val, reg);
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}
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}
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val = 0xffff407f;
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val |= 1 << (8 + priv->wan_port);
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val &= ~(1 << priv->wan_port);
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writel(val, base + MT7628_SWITCH_VMSC0);
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}
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/* Reset PHY */
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reset_assert(&priv->rst_ephy);
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reset_deassert(&priv->rst_ephy);
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mdelay(10);
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mt7628_ephy_init(priv);
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}
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static void eth_dma_start(struct mt7628_eth_dev *priv)
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{
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void __iomem *base = priv->base;
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setbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
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}
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static void eth_dma_stop(struct mt7628_eth_dev *priv)
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{
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void __iomem *base = priv->base;
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int ret;
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clrbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
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/* Wait for DMA to stop */
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ret = wait_for_bit_le32(base + PDMA_GLO_CFG,
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RX_DMA_BUSY | TX_DMA_BUSY, false,
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CFG_DMA_STOP_TIMEOUT, false);
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if (ret)
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printf("DMA stop timeout error!\n");
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}
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static int mt7628_eth_write_hwaddr(struct udevice *dev)
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{
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struct mt7628_eth_dev *priv = dev_get_priv(dev);
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void __iomem *base = priv->base;
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u8 *addr = ((struct eth_pdata *)dev_get_plat(dev))->enetaddr;
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u32 val;
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/* Set MAC address. */
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val = addr[0];
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val = (val << 8) | addr[1];
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writel(val, base + SDM_MAC_ADRH);
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val = addr[2];
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val = (val << 8) | addr[3];
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val = (val << 8) | addr[4];
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val = (val << 8) | addr[5];
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writel(val, base + SDM_MAC_ADRL);
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return 0;
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}
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static int mt7628_eth_send(struct udevice *dev, void *packet, int length)
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{
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struct mt7628_eth_dev *priv = dev_get_priv(dev);
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void __iomem *base = priv->base;
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int ret;
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int idx;
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int i;
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idx = priv->tx_dma_idx;
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/* Pad message to a minimum length */
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if (length < PADDING_LENGTH) {
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char *p = (char *)packet;
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for (i = 0; i < PADDING_LENGTH - length; i++)
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p[length + i] = 0;
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length = PADDING_LENGTH;
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}
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/* Check if buffer is ready for next TX DMA */
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ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true,
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CFG_TX_DMA_TIMEOUT, false);
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if (ret) {
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printf("TX: DMA still busy on buffer %d\n", idx);
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return ret;
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}
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flush_dcache_range((u32)packet, (u32)packet + length);
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priv->tx_ring[idx].txd1 = CPHYSADDR(packet);
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priv->tx_ring[idx].txd2 &= ~TX_DMA_PLEN0;
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priv->tx_ring[idx].txd2 |= FIELD_PREP(TX_DMA_PLEN0, length);
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priv->tx_ring[idx].txd2 &= ~TX_DMA_DONE;
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idx = (idx + 1) % NUM_TX_DESC;
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/* Make sure the writes executed at this place */
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wmb();
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writel(idx, base + TX_CTX_IDX0);
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priv->tx_dma_idx = idx;
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return 0;
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}
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static int mt7628_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct mt7628_eth_dev *priv = dev_get_priv(dev);
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u32 rxd_info;
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int length;
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int idx;
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idx = priv->rx_dma_idx;
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rxd_info = priv->rx_ring[idx].rxd2;
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if ((rxd_info & RX_DMA_DONE) == 0)
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return -EAGAIN;
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length = FIELD_GET(RX_DMA_PLEN0, priv->rx_ring[idx].rxd2);
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if (length == 0 || length > MTK_QDMA_PAGE_SIZE) {
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printf("%s: invalid length (%d bytes)\n", __func__, length);
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mt7628_eth_free_pkt(dev, NULL, 0);
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return -EIO;
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}
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*packetp = priv->rx_buf[idx];
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invalidate_dcache_range((u32)*packetp, (u32)*packetp + length);
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priv->rx_ring[idx].rxd4 = 0;
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priv->rx_ring[idx].rxd2 = RX_DMA_LSO;
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/* Make sure the writes executed at this place */
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wmb();
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return length;
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}
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static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct mt7628_eth_dev *priv = dev_get_priv(dev);
|
|
void __iomem *base = priv->base;
|
|
int idx;
|
|
|
|
idx = priv->rx_dma_idx;
|
|
|
|
/* Move point to next RXD which wants to alloc */
|
|
writel(idx, base + RX_CALC_IDX0);
|
|
|
|
/* Update to Next packet point that was received */
|
|
idx = (idx + 1) % NUM_RX_DESC;
|
|
|
|
priv->rx_dma_idx = idx;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt7628_eth_start(struct udevice *dev)
|
|
{
|
|
struct mt7628_eth_dev *priv = dev_get_priv(dev);
|
|
void __iomem *base = priv->base;
|
|
uchar packet[MTK_QDMA_PAGE_SIZE];
|
|
uchar *packetp;
|
|
int ret;
|
|
int i;
|
|
|
|
for (i = 0; i < NUM_RX_DESC; i++) {
|
|
memset((void *)&priv->rx_ring[i], 0, sizeof(priv->rx_ring[0]));
|
|
priv->rx_ring[i].rxd2 |= RX_DMA_LSO;
|
|
priv->rx_ring[i].rxd1 = CPHYSADDR(priv->rx_buf[i]);
|
|
}
|
|
|
|
for (i = 0; i < NUM_TX_DESC; i++) {
|
|
memset((void *)&priv->tx_ring[i], 0, sizeof(priv->tx_ring[0]));
|
|
priv->tx_ring[i].txd2 = TX_DMA_LS0 | TX_DMA_DONE;
|
|
priv->tx_ring[i].txd4 = FIELD_PREP(TX_DMA_PN, 1);
|
|
}
|
|
|
|
priv->rx_dma_idx = 0;
|
|
priv->tx_dma_idx = 0;
|
|
|
|
/* Make sure the writes executed at this place */
|
|
wmb();
|
|
|
|
/* disable delay interrupt */
|
|
writel(0, base + DLY_INT_CFG);
|
|
|
|
clrbits_le32(base + PDMA_GLO_CFG, 0xffff0000);
|
|
|
|
/* Tell the adapter where the TX/RX rings are located. */
|
|
writel(CPHYSADDR(&priv->rx_ring[0]), base + RX_BASE_PTR0);
|
|
writel(CPHYSADDR((u32)&priv->tx_ring[0]), base + TX_BASE_PTR0);
|
|
|
|
writel(NUM_RX_DESC, base + RX_MAX_CNT0);
|
|
writel(NUM_TX_DESC, base + TX_MAX_CNT0);
|
|
|
|
writel(priv->tx_dma_idx, base + TX_CTX_IDX0);
|
|
writel(RST_DTX_IDX0, base + PDMA_RST_IDX);
|
|
|
|
writel(NUM_RX_DESC - 1, base + RX_CALC_IDX0);
|
|
writel(RST_DRX_IDX0, base + PDMA_RST_IDX);
|
|
|
|
/* Make sure the writes executed at this place */
|
|
wmb();
|
|
eth_dma_start(priv);
|
|
|
|
if (priv->phy) {
|
|
ret = phy_startup(priv->phy);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!priv->phy->link)
|
|
return -EAGAIN;
|
|
}
|
|
|
|
/*
|
|
* The integrated switch seems to queue some received ethernet
|
|
* packets in some FIFO. Lets read the already queued packets
|
|
* out by using the receive routine, so that these old messages
|
|
* are dropped before the new xfer starts.
|
|
*/
|
|
packetp = &packet[0];
|
|
while (mt7628_eth_recv(dev, 0, &packetp) != -EAGAIN)
|
|
mt7628_eth_free_pkt(dev, packetp, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mt7628_eth_stop(struct udevice *dev)
|
|
{
|
|
struct mt7628_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
eth_dma_stop(priv);
|
|
}
|
|
|
|
static int mt7628_eth_probe(struct udevice *dev)
|
|
{
|
|
struct mt7628_eth_dev *priv = dev_get_priv(dev);
|
|
struct mii_dev *bus;
|
|
int poll_link_phy;
|
|
int ret;
|
|
int i;
|
|
|
|
/* Save frame-engine base address for later use */
|
|
priv->base = dev_remap_addr_index(dev, 0);
|
|
if (IS_ERR(priv->base))
|
|
return PTR_ERR(priv->base);
|
|
|
|
/* Save switch base address for later use */
|
|
priv->eth_sw_base = dev_remap_addr_index(dev, 1);
|
|
if (IS_ERR(priv->eth_sw_base))
|
|
return PTR_ERR(priv->eth_sw_base);
|
|
|
|
/* Reset controller */
|
|
ret = reset_get_by_name(dev, "ephy", &priv->rst_ephy);
|
|
if (ret) {
|
|
pr_err("unable to find reset controller for ethernet PHYs\n");
|
|
return ret;
|
|
}
|
|
|
|
/* WAN port will be isolated from LAN ports */
|
|
priv->wan_port = dev_read_u32_default(dev, "mediatek,wan-port", -1);
|
|
|
|
/* Put rx and tx rings into KSEG1 area (uncached) */
|
|
priv->tx_ring = (struct fe_tx_dma *)
|
|
KSEG1ADDR(memalign(ARCH_DMA_MINALIGN,
|
|
sizeof(*priv->tx_ring) * NUM_TX_DESC));
|
|
priv->rx_ring = (struct fe_rx_dma *)
|
|
KSEG1ADDR(memalign(ARCH_DMA_MINALIGN,
|
|
sizeof(*priv->rx_ring) * NUM_RX_DESC));
|
|
|
|
for (i = 0; i < NUM_RX_DESC; i++)
|
|
priv->rx_buf[i] = memalign(PKTALIGN, MTK_QDMA_PAGE_SIZE);
|
|
|
|
bus = mdio_alloc();
|
|
if (!bus) {
|
|
printf("Failed to allocate MDIO bus\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
bus->read = mt7628_mdio_read;
|
|
bus->write = mt7628_mdio_write;
|
|
snprintf(bus->name, sizeof(bus->name), dev->name);
|
|
bus->priv = (void *)priv;
|
|
|
|
ret = mdio_register(bus);
|
|
if (ret)
|
|
return ret;
|
|
|
|
poll_link_phy = dev_read_u32_default(dev, "mediatek,poll-link-phy", -1);
|
|
if (poll_link_phy >= 0) {
|
|
if (poll_link_phy >= NUM_PHYS) {
|
|
pr_err("invalid phy %d for poll-link-phy\n",
|
|
poll_link_phy);
|
|
return ret;
|
|
}
|
|
|
|
priv->phy = phy_connect(bus, poll_link_phy, dev,
|
|
PHY_INTERFACE_MODE_MII);
|
|
if (!priv->phy) {
|
|
pr_err("failed to probe phy %d\n", poll_link_phy);
|
|
return -ENODEV;
|
|
}
|
|
|
|
priv->phy->advertising = priv->phy->supported;
|
|
phy_config(priv->phy);
|
|
}
|
|
|
|
/* Switch configuration */
|
|
rt305x_esw_init(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops mt7628_eth_ops = {
|
|
.start = mt7628_eth_start,
|
|
.send = mt7628_eth_send,
|
|
.recv = mt7628_eth_recv,
|
|
.free_pkt = mt7628_eth_free_pkt,
|
|
.stop = mt7628_eth_stop,
|
|
.write_hwaddr = mt7628_eth_write_hwaddr,
|
|
};
|
|
|
|
static const struct udevice_id mt7628_eth_ids[] = {
|
|
{ .compatible = "mediatek,mt7628-eth" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(mt7628_eth) = {
|
|
.name = "mt7628_eth",
|
|
.id = UCLASS_ETH,
|
|
.of_match = mt7628_eth_ids,
|
|
.probe = mt7628_eth_probe,
|
|
.ops = &mt7628_eth_ops,
|
|
.priv_auto = sizeof(struct mt7628_eth_dev),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
};
|