mirror of
https://github.com/AsahiLinux/u-boot
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e24b58f5ed
Currently we require PHY interface mode to be known when finding/creating the PHY - the functions * phy_connect_phy_id() * phy_device_create() * create_phy_by_mask() * search_for_existing_phy() * get_phy_device_by_mask() * phy_find_by_mask() all require the interface parameter, but the only thing done with it is that it is assigned to phydev->interface. This makes it impossible to find a PHY device without overwriting the set mode. Since the interface mode is not used during .probe() and should be used at first in .config(), drop the interface parameter from these functions. Make the default value of phydev->interface (in phy_device_create()) to be PHY_INTERFACE_MODE_NA. Move the interface parameter to phy_connect_dev(), where it should be. Change all occurrences treewide. In occurrences where we don't call phy_connect_dev() for some reason (they only configure the PHY without connecting it to an ethernet controller), set phydev->interface = value from phy_find_by_mask call. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
711 lines
18 KiB
C
711 lines
18 KiB
C
/*
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* Altera 10/100/1000 triple speed ethernet mac driver
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*
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* Copyright (C) 2008 Altera Corporation.
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdt_support.h>
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#include <log.h>
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#include <memalign.h>
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#include <miiphy.h>
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#include <net.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include "altera_tse.h"
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DECLARE_GLOBAL_DATA_PTR;
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static inline void alt_sgdma_construct_descriptor(
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struct alt_sgdma_descriptor *desc,
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struct alt_sgdma_descriptor *next,
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void *read_addr,
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void *write_addr,
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u16 length_or_eop,
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int generate_eop,
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int read_fixed,
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int write_fixed_or_sop)
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{
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u8 val;
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/*
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* Mark the "next" descriptor as "not" owned by hardware. This prevents
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* The SGDMA controller from continuing to process the chain.
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*/
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next->descriptor_control = next->descriptor_control &
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~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
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memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
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desc->source = virt_to_phys(read_addr);
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desc->destination = virt_to_phys(write_addr);
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desc->next = virt_to_phys(next);
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desc->bytes_to_transfer = length_or_eop;
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/*
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* Set the descriptor control block as follows:
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* - Set "owned by hardware" bit
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* - Optionally set "generate EOP" bit
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* - Optionally set the "read from fixed address" bit
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* - Optionally set the "write to fixed address bit (which serves
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* serves as a "generate SOP" control bit in memory-to-stream mode).
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* - Set the 4-bit atlantic channel, if specified
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*
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* Note this step is performed after all other descriptor information
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* has been filled out so that, if the controller already happens to be
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* pointing at this descriptor, it will not run (via the "owned by
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* hardware" bit) until all other descriptor has been set up.
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*/
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val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
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if (generate_eop)
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val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
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if (read_fixed)
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val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
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if (write_fixed_or_sop)
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val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
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desc->descriptor_control = val;
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}
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static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
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{
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int status;
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ulong ctime;
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/* Wait for the descriptor (chain) to complete */
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ctime = get_timer(0);
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while (1) {
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status = readl(®s->status);
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if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
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break;
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if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
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status = -ETIMEDOUT;
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debug("sgdma timeout\n");
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break;
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}
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}
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/* Clear Run */
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writel(0, ®s->control);
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/* Clear status */
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writel(0xff, ®s->status);
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return status;
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}
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static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
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struct alt_sgdma_descriptor *desc)
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{
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u32 val;
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/* Point the controller at the descriptor */
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writel(virt_to_phys(desc), ®s->next_descriptor_pointer);
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/*
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* Set up SGDMA controller to:
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* - Disable interrupt generation
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* - Run once a valid descriptor is written to controller
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* - Stop on an error with any particular descriptor
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*/
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val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
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writel(val, ®s->control);
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return 0;
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}
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static void tse_adjust_link(struct altera_tse_priv *priv,
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struct phy_device *phydev)
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{
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struct alt_tse_mac *mac_dev = priv->mac_dev;
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u32 refvar;
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if (!phydev->link) {
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debug("%s: No link.\n", phydev->dev->name);
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return;
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}
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refvar = readl(&mac_dev->command_config);
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if (phydev->duplex)
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refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
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else
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refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
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switch (phydev->speed) {
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case 1000:
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refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
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refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
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break;
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case 100:
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refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
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refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
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break;
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case 10:
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refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
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refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
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break;
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}
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writel(refvar, &mac_dev->command_config);
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}
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static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
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alt_sgdma_construct_descriptor(
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tx_desc,
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tx_desc + 1,
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packet, /* read addr */
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NULL, /* write addr */
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length, /* length or EOP ,will change for each tx */
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1, /* gen eop */
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0, /* read fixed */
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1 /* write fixed or sop */
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);
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/* send the packet */
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alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
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alt_sgdma_wait_transfer(priv->sgdma_tx);
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debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
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return tx_desc->actual_bytes_transferred;
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}
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static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
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uchar **packetp)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
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int packet_length;
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if (rx_desc->descriptor_status &
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ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
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alt_sgdma_wait_transfer(priv->sgdma_rx);
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packet_length = rx_desc->actual_bytes_transferred;
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debug("recv %d bytes\n", packet_length);
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*packetp = priv->rx_buf;
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return packet_length;
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}
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return -EAGAIN;
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}
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static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
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int length)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
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alt_sgdma_construct_descriptor(
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rx_desc,
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rx_desc + 1,
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NULL, /* read addr */
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priv->rx_buf, /* write addr */
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0, /* length or EOP */
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0, /* gen eop */
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0, /* read fixed */
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0 /* write fixed or sop */
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);
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/* setup the sgdma */
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alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
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debug("recv setup\n");
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return 0;
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}
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static void altera_tse_stop_mac(struct altera_tse_priv *priv)
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{
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struct alt_tse_mac *mac_dev = priv->mac_dev;
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u32 status;
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ulong ctime;
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/* reset the mac */
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writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
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ctime = get_timer(0);
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while (1) {
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status = readl(&mac_dev->command_config);
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if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
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break;
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if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
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debug("Reset mac timeout\n");
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break;
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}
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}
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}
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static void altera_tse_stop_sgdma(struct udevice *dev)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
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struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
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struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
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int ret;
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/* clear rx desc & wait for sgdma to complete */
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rx_desc->descriptor_control = 0;
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writel(0, &rx_sgdma->control);
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ret = alt_sgdma_wait_transfer(rx_sgdma);
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if (ret == -ETIMEDOUT)
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
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&rx_sgdma->control);
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writel(0, &tx_sgdma->control);
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ret = alt_sgdma_wait_transfer(tx_sgdma);
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if (ret == -ETIMEDOUT)
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
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&tx_sgdma->control);
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}
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static void msgdma_reset(struct msgdma_csr *csr)
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{
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u32 status;
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ulong ctime;
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/* Reset mSGDMA */
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writel(MSGDMA_CSR_STAT_MASK, &csr->status);
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writel(MSGDMA_CSR_CTL_RESET, &csr->control);
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ctime = get_timer(0);
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while (1) {
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status = readl(&csr->status);
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if (!(status & MSGDMA_CSR_STAT_RESETTING))
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break;
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if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
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debug("Reset msgdma timeout\n");
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break;
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}
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}
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/* Clear status */
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writel(MSGDMA_CSR_STAT_MASK, &csr->status);
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}
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static u32 msgdma_wait(struct msgdma_csr *csr)
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{
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u32 status;
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ulong ctime;
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/* Wait for the descriptor to complete */
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ctime = get_timer(0);
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while (1) {
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status = readl(&csr->status);
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if (!(status & MSGDMA_CSR_STAT_BUSY))
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break;
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if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
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debug("sgdma timeout\n");
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break;
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}
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}
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/* Clear status */
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writel(MSGDMA_CSR_STAT_MASK, &csr->status);
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return status;
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}
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static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
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int length)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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struct msgdma_extended_desc *desc = priv->tx_desc;
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u32 tx_buf = virt_to_phys(packet);
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u32 status;
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writel(tx_buf, &desc->read_addr_lo);
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writel(0, &desc->read_addr_hi);
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writel(0, &desc->write_addr_lo);
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writel(0, &desc->write_addr_hi);
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writel(length, &desc->len);
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writel(0, &desc->burst_seq_num);
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writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
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writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
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status = msgdma_wait(priv->sgdma_tx);
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debug("sent %d bytes, status %08x\n", length, status);
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return 0;
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}
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static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
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uchar **packetp)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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struct msgdma_csr *csr = priv->sgdma_rx;
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struct msgdma_response *resp = priv->rx_resp;
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u32 level, length, status;
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level = readl(&csr->resp_fill_level);
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if (level & 0xffff) {
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length = readl(&resp->bytes_transferred);
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status = readl(&resp->status);
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debug("recv %d bytes, status %08x\n", length, status);
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*packetp = priv->rx_buf;
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return length;
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}
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return -EAGAIN;
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}
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static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
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int length)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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struct msgdma_extended_desc *desc = priv->rx_desc;
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u32 rx_buf = virt_to_phys(priv->rx_buf);
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writel(0, &desc->read_addr_lo);
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writel(0, &desc->read_addr_hi);
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writel(rx_buf, &desc->write_addr_lo);
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writel(0, &desc->write_addr_hi);
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writel(PKTSIZE_ALIGN, &desc->len);
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writel(0, &desc->burst_seq_num);
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writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
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writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
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debug("recv setup\n");
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return 0;
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}
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static void altera_tse_stop_msgdma(struct udevice *dev)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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msgdma_reset(priv->sgdma_rx);
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msgdma_reset(priv->sgdma_tx);
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}
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static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct altera_tse_priv *priv = bus->priv;
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struct alt_tse_mac *mac_dev = priv->mac_dev;
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u32 value;
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/* set mdio address */
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writel(addr, &mac_dev->mdio_phy1_addr);
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/* get the data */
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value = readl(&mac_dev->mdio_phy1[reg]);
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return value & 0xffff;
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}
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static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct altera_tse_priv *priv = bus->priv;
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struct alt_tse_mac *mac_dev = priv->mac_dev;
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/* set mdio address */
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writel(addr, &mac_dev->mdio_phy1_addr);
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/* set the data */
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writel(val, &mac_dev->mdio_phy1[reg]);
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return 0;
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}
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static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate MDIO bus\n");
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return -ENOMEM;
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}
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bus->read = tse_mdio_read;
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bus->write = tse_mdio_write;
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snprintf(bus->name, sizeof(bus->name), "%s", name);
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bus->priv = (void *)priv;
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return mdio_register(bus);
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}
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static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
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{
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struct phy_device *phydev;
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unsigned int mask = 0xffffffff;
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if (priv->phyaddr)
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mask = 1 << priv->phyaddr;
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phydev = phy_find_by_mask(priv->bus, mask);
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if (!phydev)
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return -ENODEV;
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phy_connect_dev(phydev, dev, priv->interface);
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phydev->supported &= PHY_GBIT_FEATURES;
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phydev->advertising = phydev->supported;
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priv->phydev = phydev;
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phy_config(phydev);
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return 0;
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}
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static int altera_tse_write_hwaddr(struct udevice *dev)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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struct alt_tse_mac *mac_dev = priv->mac_dev;
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struct eth_pdata *pdata = dev_get_plat(dev);
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u8 *hwaddr = pdata->enetaddr;
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u32 mac_lo, mac_hi;
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mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
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(hwaddr[1] << 8) | hwaddr[0];
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mac_hi = (hwaddr[5] << 8) | hwaddr[4];
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debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
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writel(mac_lo, &mac_dev->mac_addr_0);
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writel(mac_hi, &mac_dev->mac_addr_1);
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writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
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writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
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writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
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writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
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writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
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writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
|
|
writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
|
|
writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int altera_tse_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct altera_tse_priv *priv = dev_get_priv(dev);
|
|
unsigned long tx_buf = (unsigned long)packet;
|
|
|
|
flush_dcache_range(tx_buf, tx_buf + length);
|
|
|
|
return priv->ops->send(dev, packet, length);
|
|
}
|
|
|
|
static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct altera_tse_priv *priv = dev_get_priv(dev);
|
|
|
|
return priv->ops->recv(dev, flags, packetp);
|
|
}
|
|
|
|
static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
|
|
int length)
|
|
{
|
|
struct altera_tse_priv *priv = dev_get_priv(dev);
|
|
unsigned long rx_buf = (unsigned long)priv->rx_buf;
|
|
|
|
invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
|
|
|
|
return priv->ops->free_pkt(dev, packet, length);
|
|
}
|
|
|
|
static void altera_tse_stop(struct udevice *dev)
|
|
{
|
|
struct altera_tse_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->ops->stop(dev);
|
|
altera_tse_stop_mac(priv);
|
|
}
|
|
|
|
static int altera_tse_start(struct udevice *dev)
|
|
{
|
|
struct altera_tse_priv *priv = dev_get_priv(dev);
|
|
struct alt_tse_mac *mac_dev = priv->mac_dev;
|
|
u32 val;
|
|
int ret;
|
|
|
|
/* need to create sgdma */
|
|
debug("Configuring rx desc\n");
|
|
altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
|
|
/* start TSE */
|
|
debug("Configuring TSE Mac\n");
|
|
/* Initialize MAC registers */
|
|
writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
|
|
writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
|
|
writel(0, &mac_dev->rx_sel_full_threshold);
|
|
writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
|
|
writel(0, &mac_dev->tx_sel_full_threshold);
|
|
writel(8, &mac_dev->rx_almost_empty_threshold);
|
|
writel(8, &mac_dev->rx_almost_full_threshold);
|
|
writel(8, &mac_dev->tx_almost_empty_threshold);
|
|
writel(3, &mac_dev->tx_almost_full_threshold);
|
|
|
|
/* NO Shift */
|
|
writel(0, &mac_dev->rx_cmd_stat);
|
|
writel(0, &mac_dev->tx_cmd_stat);
|
|
|
|
/* enable MAC */
|
|
val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
|
|
writel(val, &mac_dev->command_config);
|
|
|
|
/* Start up the PHY */
|
|
ret = phy_startup(priv->phydev);
|
|
if (ret) {
|
|
debug("Could not initialize PHY %s\n",
|
|
priv->phydev->dev->name);
|
|
return ret;
|
|
}
|
|
|
|
tse_adjust_link(priv, priv->phydev);
|
|
|
|
if (!priv->phydev->link)
|
|
return -EIO;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct tse_ops tse_sgdma_ops = {
|
|
.send = altera_tse_send_sgdma,
|
|
.recv = altera_tse_recv_sgdma,
|
|
.free_pkt = altera_tse_free_pkt_sgdma,
|
|
.stop = altera_tse_stop_sgdma,
|
|
};
|
|
|
|
static const struct tse_ops tse_msgdma_ops = {
|
|
.send = altera_tse_send_msgdma,
|
|
.recv = altera_tse_recv_msgdma,
|
|
.free_pkt = altera_tse_free_pkt_msgdma,
|
|
.stop = altera_tse_stop_msgdma,
|
|
};
|
|
|
|
static int altera_tse_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct altera_tse_priv *priv = dev_get_priv(dev);
|
|
void *blob = (void *)gd->fdt_blob;
|
|
int node = dev_of_offset(dev);
|
|
const char *list, *end;
|
|
const fdt32_t *cell;
|
|
void *base, *desc_mem = NULL;
|
|
unsigned long addr, size;
|
|
int parent, addrc, sizec;
|
|
int len, idx;
|
|
int ret;
|
|
|
|
priv->dma_type = dev_get_driver_data(dev);
|
|
if (priv->dma_type == ALT_SGDMA)
|
|
priv->ops = &tse_sgdma_ops;
|
|
else
|
|
priv->ops = &tse_msgdma_ops;
|
|
/*
|
|
* decode regs. there are multiple reg tuples, and they need to
|
|
* match with reg-names.
|
|
*/
|
|
parent = fdt_parent_offset(blob, node);
|
|
fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
|
|
list = fdt_getprop(blob, node, "reg-names", &len);
|
|
if (!list)
|
|
return -ENOENT;
|
|
end = list + len;
|
|
cell = fdt_getprop(blob, node, "reg", &len);
|
|
if (!cell)
|
|
return -ENOENT;
|
|
idx = 0;
|
|
while (list < end) {
|
|
addr = fdt_translate_address((void *)blob,
|
|
node, cell + idx);
|
|
size = fdt_addr_to_cpu(cell[idx + addrc]);
|
|
base = map_physmem(addr, size, MAP_NOCACHE);
|
|
len = strlen(list);
|
|
if (strcmp(list, "control_port") == 0)
|
|
priv->mac_dev = base;
|
|
else if (strcmp(list, "rx_csr") == 0)
|
|
priv->sgdma_rx = base;
|
|
else if (strcmp(list, "rx_desc") == 0)
|
|
priv->rx_desc = base;
|
|
else if (strcmp(list, "rx_resp") == 0)
|
|
priv->rx_resp = base;
|
|
else if (strcmp(list, "tx_csr") == 0)
|
|
priv->sgdma_tx = base;
|
|
else if (strcmp(list, "tx_desc") == 0)
|
|
priv->tx_desc = base;
|
|
else if (strcmp(list, "s1") == 0)
|
|
desc_mem = base;
|
|
idx += addrc + sizec;
|
|
list += (len + 1);
|
|
}
|
|
/* decode fifo depth */
|
|
priv->rx_fifo_depth = fdtdec_get_int(blob, node,
|
|
"rx-fifo-depth", 0);
|
|
priv->tx_fifo_depth = fdtdec_get_int(blob, node,
|
|
"tx-fifo-depth", 0);
|
|
/* decode phy */
|
|
addr = fdtdec_get_int(blob, node,
|
|
"phy-handle", 0);
|
|
addr = fdt_node_offset_by_phandle(blob, addr);
|
|
priv->phyaddr = fdtdec_get_int(blob, addr,
|
|
"reg", 0);
|
|
/* init desc */
|
|
if (priv->dma_type == ALT_SGDMA) {
|
|
len = sizeof(struct alt_sgdma_descriptor) * 4;
|
|
if (!desc_mem) {
|
|
desc_mem = dma_alloc_coherent(len, &addr);
|
|
if (!desc_mem)
|
|
return -ENOMEM;
|
|
}
|
|
memset(desc_mem, 0, len);
|
|
priv->tx_desc = desc_mem;
|
|
priv->rx_desc = priv->tx_desc +
|
|
2 * sizeof(struct alt_sgdma_descriptor);
|
|
}
|
|
/* allocate recv packet buffer */
|
|
priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
|
|
if (!priv->rx_buf)
|
|
return -ENOMEM;
|
|
|
|
/* stop controller */
|
|
debug("Reset TSE & SGDMAs\n");
|
|
altera_tse_stop(dev);
|
|
|
|
/* start the phy */
|
|
priv->interface = pdata->phy_interface;
|
|
tse_mdio_init(dev->name, priv);
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
ret = tse_phy_init(priv, dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int altera_tse_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
|
|
pdata->phy_interface = dev_read_phy_mode(dev);
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops altera_tse_ops = {
|
|
.start = altera_tse_start,
|
|
.send = altera_tse_send,
|
|
.recv = altera_tse_recv,
|
|
.free_pkt = altera_tse_free_pkt,
|
|
.stop = altera_tse_stop,
|
|
.write_hwaddr = altera_tse_write_hwaddr,
|
|
};
|
|
|
|
static const struct udevice_id altera_tse_ids[] = {
|
|
{ .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
|
|
{ .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(altera_tse) = {
|
|
.name = "altera_tse",
|
|
.id = UCLASS_ETH,
|
|
.of_match = altera_tse_ids,
|
|
.ops = &altera_tse_ops,
|
|
.of_to_plat = altera_tse_of_to_plat,
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.priv_auto = sizeof(struct altera_tse_priv),
|
|
.probe = altera_tse_probe,
|
|
};
|