mirror of
https://github.com/AsahiLinux/u-boot
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0f3466f52f
Generic SDHCI driver received support for checking the busy status by
polling the DAT[0] level instead of waiting for the worst MMC switch time.
Unfortunately, it appears that this does not work for Xenon controllers
despite being a part of the standard SDHCI registers and the Armada 3720
datasheet itself telling that BIT(20) is useful for detecting the DAT[0]
busy signal.
I have tried increasing the timeout value, but I have newer managed to
catch DAT_LEVEL bits change from 0 at all.
This issue appears to hit most if not all SoC-s supported by Xenon driver,
at least A3720, A8040 and CN9130 have non working eMMC currently.
So, until a better solution is found drop the wait_dat0 OP for Xenon.
I was able to only test it on A3720, but it should work for others as well.
Fixes: 40e6f52454
("drivers: mmc: Add wait_dat0 support for sdhci driver")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Stefan Roese <sr@denx.de>
582 lines
15 KiB
C
582 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
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*
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* Copyright (C) 2016 Marvell, All Rights Reserved.
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*
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* Author: Victor Gu <xigu@marvell.com>
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* Date: 2016-8-24
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*
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* Included parts of the Linux driver version which was written by:
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* Hu Ziji <huziji@marvell.com>
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*
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* Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
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* Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <asm/global_data.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Register Offset of SD Host Controller SOCP self-defined register */
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#define SDHC_SYS_CFG_INFO 0x0104
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#define SLOT_TYPE_SDIO_SHIFT 24
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#define SLOT_TYPE_EMMC_MASK 0xFF
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#define SLOT_TYPE_EMMC_SHIFT 16
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#define SLOT_TYPE_SD_SDIO_MMC_MASK 0xFF
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#define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8
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#define NR_SUPPORTED_SLOT_MASK 0x7
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#define SDHC_SYS_OP_CTRL 0x0108
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#define AUTO_CLKGATE_DISABLE_MASK BIT(20)
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#define SDCLK_IDLEOFF_ENABLE_SHIFT 8
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#define SLOT_ENABLE_SHIFT 0
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#define SDHC_SYS_EXT_OP_CTRL 0x010C
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#define MASK_CMD_CONFLICT_ERROR BIT(8)
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#define SDHC_SLOT_EMMC_CTRL 0x0130
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#define ENABLE_DATA_STROBE_SHIFT 24
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#define SET_EMMC_RSTN_SHIFT 16
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#define EMMC_VCCQ_MASK 0x3
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#define EMMC_VCCQ_1_8V 0x1
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#define EMMC_VCCQ_1_2V 0x2
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#define EMMC_VCCQ_3_3V 0x3
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#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144
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/* retuning compatible */
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#define RETUNING_COMPATIBLE 0x1
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/* Xenon specific Mode Select value */
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#define XENON_SDHCI_CTRL_HS200 0x5
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#define XENON_SDHCI_CTRL_HS400 0x6
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#define EMMC_PHY_REG_BASE 0x170
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#define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE
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#define OUTPUT_QSN_PHASE_SELECT BIT(17)
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#define SAMPL_INV_QSP_PHASE_SELECT BIT(18)
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#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
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#define EMMC_PHY_SLOW_MODE BIT(29)
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#define PHY_INITIALIZAION BIT(31)
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#define WAIT_CYCLE_BEFORE_USING_MASK 0xf
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#define WAIT_CYCLE_BEFORE_USING_SHIFT 12
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#define FC_SYNC_EN_DURATION_MASK 0xf
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#define FC_SYNC_EN_DURATION_SHIFT 8
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#define FC_SYNC_RST_EN_DURATION_MASK 0xf
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#define FC_SYNC_RST_EN_DURATION_SHIFT 4
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#define FC_SYNC_RST_DURATION_MASK 0xf
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#define FC_SYNC_RST_DURATION_SHIFT 0
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#define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4)
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#define DQ_ASYNC_MODE BIT(4)
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#define DQ_DDR_MODE_SHIFT 8
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#define DQ_DDR_MODE_MASK 0xff
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#define CMD_DDR_MODE BIT(16)
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#define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8)
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#define REC_EN_SHIFT 24
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#define REC_EN_MASK 0xf
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#define FC_DQ_RECEN BIT(24)
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#define FC_CMD_RECEN BIT(25)
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#define FC_QSP_RECEN BIT(26)
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#define FC_QSN_RECEN BIT(27)
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#define OEN_QSN BIT(28)
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#define AUTO_RECEN_CTRL BIT(30)
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#define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc)
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#define EMMC5_1_FC_QSP_PD BIT(9)
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#define EMMC5_1_FC_QSP_PU BIT(25)
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#define EMMC5_1_FC_CMD_PD BIT(8)
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#define EMMC5_1_FC_CMD_PU BIT(24)
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#define EMMC5_1_FC_DQ_PD 0xff
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#define EMMC5_1_FC_DQ_PU (0xff << 16)
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#define SDHCI_RETUNE_EVT_INTSIG 0x00001000
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/* Hyperion only have one slot 0 */
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#define XENON_MMC_SLOT_ID_HYPERION 0
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#define XENON_MMC_MAX_CLK 400000000
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#define XENON_MMC_3V3_UV 3300000
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#define XENON_MMC_1V8_UV 1800000
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enum soc_pad_ctrl_type {
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SOC_PAD_SD,
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SOC_PAD_FIXED_1_8V,
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};
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struct xenon_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct xenon_sdhci_priv {
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struct sdhci_host host;
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u8 timing;
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unsigned int clock;
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void *pad_ctrl_reg;
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int pad_type;
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struct udevice *vqmmc;
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};
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static int xenon_mmc_phy_init(struct sdhci_host *host)
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{
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struct xenon_sdhci_priv *priv = host->mmc->priv;
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u32 clock = priv->clock;
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u32 time;
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u32 var;
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/* Enable QSP PHASE SELECT */
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var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
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var |= SAMPL_INV_QSP_PHASE_SELECT;
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if ((priv->timing == MMC_TIMING_UHS_SDR50) ||
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(priv->timing == MMC_TIMING_UHS_SDR25) ||
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(priv->timing == MMC_TIMING_UHS_SDR12) ||
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(priv->timing == MMC_TIMING_SD_HS) ||
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(priv->timing == MMC_TIMING_LEGACY))
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var |= EMMC_PHY_SLOW_MODE;
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sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
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/* Poll for host MMC PHY clock init to be stable */
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/* Wait up to 10ms */
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time = 100;
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while (time--) {
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var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
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if (var & SDHCI_CLOCK_INT_STABLE)
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break;
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udelay(100);
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}
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if (time <= 0) {
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pr_err("Failed to enable MMC internal clock in time\n");
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return -ETIMEDOUT;
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}
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/* Init PHY */
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var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
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var |= PHY_INITIALIZAION;
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sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
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if (clock == 0) {
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/* Use the possibly slowest bus frequency value */
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clock = 100000;
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}
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/* Poll for host eMMC PHY init to complete */
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/* Wait up to 10ms */
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time = 100;
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while (time--) {
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var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
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var &= PHY_INITIALIZAION;
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if (!var)
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break;
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/* wait for host eMMC PHY init to complete */
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udelay(100);
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}
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if (time <= 0) {
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pr_err("Failed to init MMC PHY in time\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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#define ARMADA_3700_SOC_PAD_1_8V 0x1
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#define ARMADA_3700_SOC_PAD_3_3V 0x0
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static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host)
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{
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struct xenon_sdhci_priv *priv = host->mmc->priv;
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if (priv->pad_type == SOC_PAD_FIXED_1_8V)
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writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg);
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else if (priv->pad_type == SOC_PAD_SD)
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writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
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}
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static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host *host)
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{
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struct xenon_sdhci_priv *priv = host->mmc->priv;
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u8 voltage;
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u32 ctrl;
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int ret = 0;
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/* If there is no vqmmc regulator, return */
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if (!priv->vqmmc)
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return 0;
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if (priv->pad_type == SOC_PAD_FIXED_1_8V) {
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/* Switch to 1.8v */
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ret = regulator_set_value(priv->vqmmc,
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XENON_MMC_1V8_UV);
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} else if (priv->pad_type == SOC_PAD_SD) {
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/* Get voltage info */
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voltage = sdhci_readb(host, SDHCI_POWER_CONTROL);
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voltage &= ~SDHCI_POWER_ON;
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if (voltage == SDHCI_POWER_330) {
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/* Switch to 3.3v */
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ret = regulator_set_value(priv->vqmmc,
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XENON_MMC_3V3_UV);
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} else {
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/* Switch to 1.8v */
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ret = regulator_set_value(priv->vqmmc,
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XENON_MMC_1V8_UV);
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}
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}
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/* Set VCCQ, eMMC mode: 1.8V; SD/SDIO mode: 3.3V */
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ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL);
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if (IS_SD(host->mmc))
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ctrl |= EMMC_VCCQ_3_3V;
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else
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ctrl |= EMMC_VCCQ_1_8V;
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sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL);
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if (ret)
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printf("Signal voltage switch fail\n");
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return ret;
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}
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static void xenon_mmc_phy_set(struct sdhci_host *host)
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{
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struct xenon_sdhci_priv *priv = host->mmc->priv;
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u32 var;
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/* Setup pad, set bit[30], bit[28] and bits[26:24] */
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var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);
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var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN |
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FC_CMD_RECEN | FC_DQ_RECEN;
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sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);
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/* Set CMD and DQ Pull Up */
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var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);
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var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU);
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var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);
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sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);
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/*
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* If timing belongs to high speed, set bit[17] of
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* EMMC_PHY_TIMING_ADJUST register
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*/
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if ((priv->timing == MMC_TIMING_MMC_HS400) ||
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(priv->timing == MMC_TIMING_MMC_HS200) ||
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(priv->timing == MMC_TIMING_UHS_SDR50) ||
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(priv->timing == MMC_TIMING_UHS_SDR104) ||
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(priv->timing == MMC_TIMING_UHS_DDR50) ||
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(priv->timing == MMC_TIMING_UHS_SDR25) ||
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(priv->timing == MMC_TIMING_MMC_DDR52)) {
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var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
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var |= OUTPUT_QSN_PHASE_SELECT;
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sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
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}
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/*
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* When setting EMMC_PHY_FUNC_CONTROL register,
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* SD clock should be disabled
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*/
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var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
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var &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
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var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
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if (host->mmc->ddr_mode) {
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var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
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} else {
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var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |
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CMD_DDR_MODE);
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}
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sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);
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/* Enable bus clock */
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var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
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var |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
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xenon_mmc_phy_init(host);
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}
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/* Enable/Disable the Auto Clock Gating function of this slot */
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static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable)
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{
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u32 var;
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var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
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if (enable)
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var &= ~AUTO_CLKGATE_DISABLE_MASK;
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else
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var |= AUTO_CLKGATE_DISABLE_MASK;
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sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
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}
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#define SLOT_MASK(slot) BIT(slot)
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/* Enable specific slot */
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static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot)
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{
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u32 var;
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var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
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var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;
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sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
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}
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/* Disable specific slot */
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static void xenon_mmc_disable_slot(struct sdhci_host *host, u8 slot)
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{
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u32 var;
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var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
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var &= ~(SLOT_MASK(slot) << SLOT_ENABLE_SHIFT);
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sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
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}
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/* Enable Parallel Transfer Mode */
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static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot)
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{
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u32 var;
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var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
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var |= SLOT_MASK(slot);
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sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);
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}
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static void xenon_mmc_disable_tuning(struct sdhci_host *host, u8 slot)
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{
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u32 var;
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/* Clear the Re-Tuning Request functionality */
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var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);
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var &= ~RETUNING_COMPATIBLE;
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sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);
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/* Clear the Re-tuning Event Signal Enable */
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var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
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var &= ~SDHCI_RETUNE_EVT_INTSIG;
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sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);
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}
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/* Mask command conflict error */
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static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
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{
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u32 reg;
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reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
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reg |= MASK_CMD_CONFLICT_ERROR;
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sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL);
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}
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/* Platform specific function for post set_ios configuration */
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static int xenon_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct xenon_sdhci_priv *priv = host->mmc->priv;
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uint speed = host->mmc->tran_speed;
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int pwr_18v = 0;
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/*
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* Signal Voltage Switching is only applicable for Host Controllers
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* v3.00 and above.
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*/
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if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
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xenon_mmc_start_signal_voltage_switch(host);
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if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
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SDHCI_POWER_180)
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pwr_18v = 1;
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/* Set timing variable according to the configured speed */
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if (IS_SD(host->mmc)) {
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/* SD/SDIO */
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if (pwr_18v) {
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if (host->mmc->ddr_mode)
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priv->timing = MMC_TIMING_UHS_DDR50;
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else if (speed <= 25000000)
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priv->timing = MMC_TIMING_UHS_SDR25;
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else
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priv->timing = MMC_TIMING_UHS_SDR50;
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} else {
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if (speed <= 25000000)
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priv->timing = MMC_TIMING_LEGACY;
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else
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priv->timing = MMC_TIMING_SD_HS;
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}
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} else {
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/* eMMC */
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if (host->mmc->ddr_mode)
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priv->timing = MMC_TIMING_MMC_DDR52;
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else if (speed <= 26000000)
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priv->timing = MMC_TIMING_LEGACY;
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else
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priv->timing = MMC_TIMING_MMC_HS;
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}
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/* Re-init the PHY */
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xenon_mmc_phy_set(host);
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return 0;
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}
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/* Install a driver specific handler for post set_ios configuration */
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static const struct sdhci_ops xenon_sdhci_ops = {
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.set_ios_post = xenon_sdhci_set_ios_post
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};
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static struct dm_mmc_ops xenon_mmc_ops;
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static int xenon_sdhci_probe(struct udevice *dev)
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{
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struct xenon_sdhci_plat *plat = dev_get_plat(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct xenon_sdhci_priv *priv = dev_get_priv(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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int ret;
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host->mmc = &plat->mmc;
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host->mmc->priv = host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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xenon_mmc_ops = sdhci_ops;
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xenon_mmc_ops.wait_dat0 = NULL;
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/* Set quirks */
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
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/* Set default timing */
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priv->timing = MMC_TIMING_LEGACY;
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/* Get the vqmmc regulator if there is */
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device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc);
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/* Set the initial voltage value to 3.3V if there is regulator */
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if (priv->vqmmc) {
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ret = regulator_set_value(priv->vqmmc,
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XENON_MMC_3V3_UV);
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if (ret) {
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printf("Failed to set VQMMC regulator to 3.3V\n");
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return ret;
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}
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}
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/* Disable auto clock gating during init */
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xenon_mmc_set_acg(host, false);
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/* Enable slot */
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xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
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/*
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* Set default power on SoC PHY PAD register (currently only
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* available on the Armada 3700)
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*/
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if (priv->pad_ctrl_reg)
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armada_3700_soc_pad_voltage_set(host);
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host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
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ret = mmc_of_parse(dev, &plat->cfg);
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if (ret)
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return ret;
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host->ops = &xenon_sdhci_ops;
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host->max_clk = XENON_MMC_MAX_CLK;
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ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0);
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if (ret)
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return ret;
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ret = sdhci_probe(dev);
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if (ret)
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return ret;
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/* Enable parallel transfer */
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xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION);
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/* Disable tuning functionality of this slot */
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xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION);
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/* Enable auto clock gating after init */
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xenon_mmc_set_acg(host, true);
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xenon_mask_cmd_conflict_err(host);
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return ret;
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}
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static int xenon_sdhci_remove(struct udevice *dev)
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{
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struct sdhci_host *host = dev_get_priv(dev);
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xenon_mmc_disable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
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return 0;
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}
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static int xenon_sdhci_of_to_plat(struct udevice *dev)
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{
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struct sdhci_host *host = dev_get_priv(dev);
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struct xenon_sdhci_priv *priv = dev_get_priv(dev);
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const char *name;
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host->name = dev->name;
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host->ioaddr = dev_read_addr_ptr(dev);
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if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
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priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
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name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
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NULL);
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if (name) {
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if (0 == strncmp(name, "sd", 2)) {
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priv->pad_type = SOC_PAD_SD;
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} else if (0 == strncmp(name, "fixed-1-8v", 10)) {
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priv->pad_type = SOC_PAD_FIXED_1_8V;
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} else {
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printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
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return -EINVAL;
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}
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}
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return 0;
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}
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static int xenon_sdhci_bind(struct udevice *dev)
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{
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struct xenon_sdhci_plat *plat = dev_get_plat(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id xenon_sdhci_ids[] = {
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{ .compatible = "marvell,armada-8k-sdhci",},
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{ .compatible = "marvell,armada-3700-sdhci",},
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{ }
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};
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U_BOOT_DRIVER(xenon_sdhci_drv) = {
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.name = "xenon_sdhci",
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.id = UCLASS_MMC,
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.of_match = xenon_sdhci_ids,
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.of_to_plat = xenon_sdhci_of_to_plat,
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.ops = &xenon_mmc_ops,
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.bind = xenon_sdhci_bind,
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.probe = xenon_sdhci_probe,
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.remove = xenon_sdhci_remove,
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.priv_auto = sizeof(struct xenon_sdhci_priv),
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.plat_auto = sizeof(struct xenon_sdhci_plat),
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};
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