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https://github.com/AsahiLinux/u-boot
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d11f0dac30
The get_mmc_clk ops is expected to set a clock rate and return the configured rate as an unsigned value. However, if clk_set_rate fails, e.g. using a fixed rate clock, a negative error value is returned. The mmc core will treat this as a valid unsigned rate and tries to configure a divider based on this bogus clock rate. Use 0 as the return value when setting clock rate fails, the mmc core will configure to use bypass mode instead of using a bogus divider. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
193 lines
4.9 KiB
C
193 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2013 Google, Inc
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <dwmmc.h>
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#include <errno.h>
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#include <log.h>
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#include <mapmem.h>
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#include <pwrseq.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/periph.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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struct rockchip_mmc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3288_dw_mshc dtplat;
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#endif
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct rockchip_dwmmc_priv {
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struct clk clk;
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struct dwmci_host host;
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int fifo_depth;
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bool fifo_mode;
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u32 minmax[2];
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};
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static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
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{
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struct udevice *dev = host->priv;
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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int ret;
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/*
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* The clock frequency chosen here affects CLKDIV in the dw_mmc core.
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* That can be either 0 or 1, but it must be set to 1 for eMMC DDR52
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* 8-bit mode. It will be set to 0 for all other modes.
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*/
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if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8)
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freq *= 2;
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ret = clk_set_rate(&priv->clk, freq);
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if (ret < 0) {
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debug("%s: err=%d\n", __func__, ret);
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return 0;
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}
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return freq;
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}
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static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
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{
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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if (!CONFIG_IS_ENABLED(OF_REAL))
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return 0;
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host->name = dev->name;
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host->ioaddr = dev_read_addr_ptr(dev);
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host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
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host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
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host->priv = dev;
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/* use non-removeable as sdcard and emmc as judgement */
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if (dev_read_bool(dev, "non-removable"))
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host->dev_index = 0;
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else
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host->dev_index = 1;
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priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
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if (priv->fifo_depth < 0)
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return -EINVAL;
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priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
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#ifdef CONFIG_SPL_BUILD
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if (!priv->fifo_mode)
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priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
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#endif
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/*
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* 'clock-freq-min-max' is deprecated
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* (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
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*/
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if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
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int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
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if (val < 0)
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return val;
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priv->minmax[0] = 400000; /* 400 kHz */
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priv->minmax[1] = val;
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} else {
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debug("%s: 'clock-freq-min-max' property was deprecated.\n",
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__func__);
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}
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return 0;
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}
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static int rockchip_dwmmc_probe(struct udevice *dev)
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{
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struct rockchip_mmc_plat *plat = dev_get_plat(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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int ret;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
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host->name = dev->name;
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host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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host->buswidth = dtplat->bus_width;
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host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
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host->priv = dev;
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host->dev_index = 0;
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priv->fifo_depth = dtplat->fifo_depth;
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priv->fifo_mode = dtplat->u_boot_spl_fifo_mode;
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priv->minmax[0] = 400000; /* 400 kHz */
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priv->minmax[1] = dtplat->max_frequency;
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ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
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if (ret < 0)
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return ret;
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#else
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ret = clk_get_by_index(dev, 1, &priv->clk);
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if (ret < 0)
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return ret;
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#endif
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host->fifoth_val = MSIZE(0x2) |
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RX_WMARK(priv->fifo_depth / 2 - 1) |
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TX_WMARK(priv->fifo_depth / 2);
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host->fifo_mode = priv->fifo_mode;
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#ifdef CONFIG_MMC_PWRSEQ
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/* Enable power if needed */
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ret = mmc_pwrseq_get_power(dev, &plat->cfg);
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if (!ret) {
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ret = pwrseq_set_power(plat->cfg.pwr_dev, true);
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if (ret)
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return ret;
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}
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#endif
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dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
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host->mmc = &plat->mmc;
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host->mmc->priv = &priv->host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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return dwmci_probe(dev);
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}
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static int rockchip_dwmmc_bind(struct udevice *dev)
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{
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struct rockchip_mmc_plat *plat = dev_get_plat(dev);
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return dwmci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id rockchip_dwmmc_ids[] = {
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{ .compatible = "rockchip,rk2928-dw-mshc" },
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{ .compatible = "rockchip,rk3288-dw-mshc" },
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{ }
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};
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U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = {
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.name = "rockchip_rk3288_dw_mshc",
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.id = UCLASS_MMC,
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.of_match = rockchip_dwmmc_ids,
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.of_to_plat = rockchip_dwmmc_of_to_plat,
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.ops = &dm_dwmci_ops,
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.bind = rockchip_dwmmc_bind,
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.probe = rockchip_dwmmc_probe,
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.priv_auto = sizeof(struct rockchip_dwmmc_priv),
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.plat_auto = sizeof(struct rockchip_mmc_plat),
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};
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DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk2928_dw_mshc)
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DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
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DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc)
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