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https://github.com/AsahiLinux/u-boot
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76cffd5795
Add tuning functionality which is needed for HS200 mode. For HS200, program the correct needed 1.8 voltage Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
327 lines
9 KiB
C
327 lines
9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Broadcom.
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <asm/global_data.h>
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#include "mmc_private.h"
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#include <linux/delay.h>
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#define MAX_TUNING_LOOP 40
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DECLARE_GLOBAL_DATA_PTR;
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struct sdhci_iproc_host {
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struct sdhci_host host;
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u32 shadow_cmd;
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u32 shadow_blk;
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};
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#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
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static inline struct sdhci_iproc_host *to_iproc(struct sdhci_host *host)
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{
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return (struct sdhci_iproc_host *)host;
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}
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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static u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
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{
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u32 val = readl(host->ioaddr + reg);
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
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printf("%s %d: readl [0x%02x] 0x%08x\n",
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host->name, host->index, reg, val);
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#endif
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return val;
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}
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static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
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{
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u32 val = sdhci_iproc_readl(host, (reg & ~3));
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u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
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return word;
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}
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static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
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{
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u32 val = sdhci_iproc_readl(host, (reg & ~3));
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u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
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return byte;
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}
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static void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
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{
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u32 clock = 0;
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
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printf("%s %d: writel [0x%02x] 0x%08x\n",
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host->name, host->index, reg, val);
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#endif
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writel(val, host->ioaddr + reg);
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if (host->mmc)
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clock = host->mmc->clock;
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if (clock <= 400000) {
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/* Round up to micro-second four SD clock delay */
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if (clock)
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udelay((4 * 1000000 + clock - 1) / clock);
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else
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udelay(10);
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}
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}
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/*
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* The Arasan has a bugette whereby it may lose the content of successive
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* writes to the same register that are within two SD-card clock cycles of
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* each other (a clock domain crossing problem). The data
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* register does not have this problem, which is just as well - otherwise we'd
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* have to nobble the DMA engine too.
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*
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* This wouldn't be a problem with the code except that we can only write the
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* controller with 32-bit writes. So two different 16-bit registers are
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* written back to back creates the problem.
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*
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* In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
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* are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
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* The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
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* the work around can be further optimized. We can keep shadow values of
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* BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
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* Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
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* by the TRANSFER+COMMAND in another 32-bit write.
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*/
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static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_iproc_host *iproc_host = to_iproc(host);
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u32 word_shift = REG_OFFSET_IN_BITS(reg);
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u32 mask = 0xffff << word_shift;
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u32 oldval, newval;
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if (reg == SDHCI_COMMAND) {
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/* Write the block now as we are issuing a command */
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if (iproc_host->shadow_blk != 0) {
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sdhci_iproc_writel(host, iproc_host->shadow_blk,
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SDHCI_BLOCK_SIZE);
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iproc_host->shadow_blk = 0;
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}
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oldval = iproc_host->shadow_cmd;
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} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
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/* Block size and count are stored in shadow reg */
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oldval = iproc_host->shadow_blk;
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} else {
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/* Read reg, all other registers are not shadowed */
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oldval = sdhci_iproc_readl(host, (reg & ~3));
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}
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newval = (oldval & ~mask) | (val << word_shift);
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if (reg == SDHCI_TRANSFER_MODE) {
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/* Save the transfer mode until the command is issued */
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iproc_host->shadow_cmd = newval;
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} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
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/* Save the block info until the command is issued */
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iproc_host->shadow_blk = newval;
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} else {
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/* Command or other regular 32-bit write */
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sdhci_iproc_writel(host, newval, reg & ~3);
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}
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}
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static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
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u32 byte_shift = REG_OFFSET_IN_BITS(reg);
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u32 mask = 0xff << byte_shift;
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u32 newval = (oldval & ~mask) | (val << byte_shift);
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sdhci_iproc_writel(host, newval, reg & ~3);
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}
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#endif
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static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
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{
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struct mmc *mmc = (struct mmc *)host->mmc;
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u32 ctrl;
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if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl |= SDHCI_CTRL_VDD_180;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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}
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sdhci_set_uhs_timing(host);
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return 0;
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}
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static void sdhci_start_tuning(struct sdhci_host *host)
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{
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u32 ctrl;
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl |= SDHCI_CTRL_EXEC_TUNING;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
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}
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static void sdhci_end_tuning(struct sdhci_host *host)
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{
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/* Enable only interrupts served by the SD controller */
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sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
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SDHCI_INT_ENABLE);
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/* Mask all sdhci interrupt sources */
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sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
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}
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static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode)
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{
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struct mmc_cmd cmd;
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u32 ctrl;
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u32 blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
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struct sdhci_host *host = dev_get_priv(mmc->dev);
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char tuning_loop_counter = MAX_TUNING_LOOP;
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int ret = 0;
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sdhci_start_tuning(host);
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cmd.cmdidx = opcode;
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cmd.resp_type = MMC_RSP_R1;
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cmd.cmdarg = 0;
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if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
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blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
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sdhci_writew(host, blocksize, SDHCI_BLOCK_SIZE);
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sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
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sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
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do {
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mmc_send_cmd(mmc, &cmd, NULL);
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if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
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/*
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* For tuning command, do not do busy loop. As tuning
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* is happening (CLK-DATA latching for setup/hold time
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* requirements), give time to complete
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*/
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udelay(1);
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (tuning_loop_counter-- == 0)
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break;
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} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
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if (tuning_loop_counter < 0 || (!(ctrl & SDHCI_CTRL_TUNED_CLK))) {
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ctrl &= ~(SDHCI_CTRL_TUNED_CLK | SDHCI_CTRL_EXEC_TUNING);
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sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
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printf("%s:Tuning failed, opcode = 0x%02x\n", __func__, opcode);
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ret = -EIO;
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}
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sdhci_end_tuning(host);
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return ret;
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}
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static struct sdhci_ops sdhci_platform_ops = {
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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.read_l = sdhci_iproc_readl,
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.read_w = sdhci_iproc_readw,
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.read_b = sdhci_iproc_readb,
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.write_l = sdhci_iproc_writel,
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.write_w = sdhci_iproc_writew,
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.write_b = sdhci_iproc_writeb,
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#endif
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.set_ios_post = sdhci_iproc_set_ios_post,
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.platform_execute_tuning = sdhci_iproc_execute_tuning,
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};
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struct iproc_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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static int iproc_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct iproc_sdhci_plat *plat = dev_get_plat(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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struct sdhci_iproc_host *iproc_host;
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int node = dev_of_offset(dev);
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u32 f_min_max[2];
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int ret;
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iproc_host = malloc(sizeof(struct sdhci_iproc_host));
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if (!iproc_host) {
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printf("%s: sdhci host malloc fail!\n", __func__);
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return -ENOMEM;
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}
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iproc_host->shadow_cmd = 0;
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iproc_host->shadow_blk = 0;
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host->name = dev->name;
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host->ioaddr = dev_read_addr_ptr(dev);
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host->quirks = SDHCI_QUIRK_BROKEN_R1B;
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host->host_caps = MMC_MODE_DDR_52MHz;
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host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
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host->ops = &sdhci_platform_ops;
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host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
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ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
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"clock-freq-min-max", f_min_max, 2);
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if (ret) {
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printf("sdhci: clock-freq-min-max not found\n");
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free(iproc_host);
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return ret;
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}
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host->max_clk = f_min_max[1];
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host->bus_width = fdtdec_get_int(gd->fdt_blob,
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dev_of_offset(dev), "bus-width", 4);
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/* Update host_caps for 8 bit bus width */
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if (host->bus_width == 8)
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host->host_caps |= MMC_MODE_8BIT;
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memcpy(&iproc_host->host, host, sizeof(struct sdhci_host));
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iproc_host->host.mmc = &plat->mmc;
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iproc_host->host.mmc->dev = dev;
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iproc_host->host.mmc->priv = &iproc_host->host;
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upriv->mmc = iproc_host->host.mmc;
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ret = sdhci_setup_cfg(&plat->cfg, &iproc_host->host,
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f_min_max[1], f_min_max[0]);
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if (ret) {
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free(iproc_host);
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return ret;
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}
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return sdhci_probe(dev);
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}
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static int iproc_sdhci_bind(struct udevice *dev)
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{
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struct iproc_sdhci_plat *plat = dev_get_plat(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id iproc_sdhci_ids[] = {
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{ .compatible = "brcm,iproc-sdhci" },
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{ }
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};
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U_BOOT_DRIVER(iproc_sdhci_drv) = {
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.name = "iproc_sdhci",
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.id = UCLASS_MMC,
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.of_match = iproc_sdhci_ids,
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.ops = &sdhci_ops,
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.bind = iproc_sdhci_bind,
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.probe = iproc_sdhci_probe,
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.priv_auto = sizeof(struct sdhci_host),
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.plat_auto = sizeof(struct iproc_sdhci_plat),
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};
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