mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 11:00:15 +00:00
0478dac62a
At this point in the conversion there should be no need to have logic to disable some symbol during the SPL build as all symbols should have an SPL counterpart. The main real changes done here are that we now must make proper use of CONFIG_IS_ENABLED(DM_SERIAL) rather than many of the odd tricks we developed prior to CONFIG_IS_ENABLED() being available. Signed-off-by: Tom Rini <trini@konsulko.com>
633 lines
14 KiB
C
633 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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#include <command.h>
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#include <gsc.h>
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#include <i2c.h>
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#include <rtc.h>
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#include <asm/unaligned.h>
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#include <linux/delay.h>
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#include <dm/device.h>
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#include <dm/device-internal.h>
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#include <dm/ofnode.h>
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#include <dm/read.h>
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#define GSC_BUSNO 0
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#define GSC_SC_ADDR 0x20
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#define GSC_HWMON_ADDR 0x29
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#define GSC_RTC_ADDR 0x68
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/* System Controller registers */
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enum {
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GSC_SC_CTRL0 = 0,
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GSC_SC_CTRL1 = 1,
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GSC_SC_TIME = 2,
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GSC_SC_TIME_ADD = 6,
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GSC_SC_STATUS = 10,
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GSC_SC_FWCRC = 12,
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GSC_SC_FWVER = 14,
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GSC_SC_WP = 15,
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GSC_SC_RST_CAUSE = 16,
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GSC_SC_THERM_PROTECT = 19,
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};
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/* System Controller Control1 bits */
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enum {
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GSC_SC_CTRL1_SLEEP_EN = 0, /* 1 = enable sleep */
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GSC_SC_CTRL1_SLEEP_ACTIVATE = 1, /* 1 = activate sleep */
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GSC_SC_CTRL1_SLEEP_ADD = 2, /* 1 = latch and add sleep time */
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GSC_SC_CTRL1_SLEEP_NOWAKEPB = 3, /* 1 = do not wake on sleep on button press */
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GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */
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GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */
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GSC_SC_CTRL1_BOOT_CHK = 6, /* 1 = enable alt boot check */
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GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */
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};
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/* System Controller Interrupt bits */
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enum {
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GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
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GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
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GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
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GSC_SC_IRQ_GPIO = 4, /* GPIO change */
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GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
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GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
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GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
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};
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/* System Controller WP bits */
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enum {
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GSC_SC_WP_ALL = 0, /* Write Protect All EEPROM regions */
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GSC_SC_WP_BOARDINFO = 1, /* Write Protect Board Info region */
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};
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/* System Controller Reset Cause */
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enum {
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GSC_SC_RST_CAUSE_VIN = 0,
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GSC_SC_RST_CAUSE_PB = 1,
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GSC_SC_RST_CAUSE_WDT = 2,
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GSC_SC_RST_CAUSE_CPU = 3,
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GSC_SC_RST_CAUSE_TEMP_LOCAL = 4,
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GSC_SC_RST_CAUSE_TEMP_REMOTE = 5,
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GSC_SC_RST_CAUSE_SLEEP = 6,
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GSC_SC_RST_CAUSE_BOOT_WDT = 7,
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GSC_SC_RST_CAUSE_BOOT_WDT_MAN = 8,
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GSC_SC_RST_CAUSE_SOFT_PWR = 9,
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GSC_SC_RST_CAUSE_MAX = 10,
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};
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct gsc_priv {
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int gscver;
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int fwver;
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int fwcrc;
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struct udevice *hwmon;
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struct udevice *rtc;
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};
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/*
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* GSCv2 will fail to ACK an I2C transaction if it is busy, which can occur
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* during its 1HZ timer tick while reading ADC's. When this does occur,
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* it will never be busy longer than 2 back-to-back transfers so retry 3 times.
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*/
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static int gsc_i2c_read(struct udevice *dev, uint addr, u8 *buf, int len)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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int retry = (priv->gscver == 3) ? 1 : 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = dm_i2c_read(dev, addr, buf, len);
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if (!ret)
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break;
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if (ret != -EREMOTEIO)
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break;
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mdelay(10);
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}
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return ret;
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}
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static int gsc_i2c_write(struct udevice *dev, uint addr, const u8 *buf, int len)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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int retry = (priv->gscver == 3) ? 1 : 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = dm_i2c_write(dev, addr, buf, len);
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if (!ret)
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break;
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if (ret != -EREMOTEIO)
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break;
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mdelay(10);
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}
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return ret;
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}
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static struct udevice *gsc_get_dev(int busno, int slave)
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{
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struct udevice *dev, *bus;
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int ret;
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ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
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if (ret)
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return NULL;
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ret = dm_i2c_probe(bus, slave, 0, &dev);
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if (ret)
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return NULL;
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return dev;
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}
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static int gsc_thermal_get_info(struct udevice *dev, u8 *outreg, int *tmax, bool *enable)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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int ret;
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u8 reg;
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if (priv->gscver > 2 && priv->fwver > 52) {
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ret = gsc_i2c_read(dev, GSC_SC_THERM_PROTECT, ®, 1);
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if (!ret) {
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if (outreg)
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*outreg = reg;
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if (tmax) {
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*tmax = ((reg & 0xf8) >> 3) * 2;
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if (*tmax)
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*tmax += 70;
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else
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*tmax = 120;
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}
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if (enable)
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*enable = reg & 1;
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}
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} else {
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ret = -ENODEV;
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}
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return ret;
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}
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static int gsc_thermal_get_temp(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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u32 reg, mode, val;
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const char *label;
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ofnode node;
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u8 buf[2];
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ofnode_for_each_subnode(node, dev_read_subnode(dev, "adc")) {
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if (ofnode_read_u32(node, "reg", ®))
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reg = -1;
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if (ofnode_read_u32(node, "gw,mode", &mode))
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mode = -1;
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label = ofnode_read_string(node, "label");
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if ((reg == -1) || (mode == -1) || !label)
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continue;
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if (mode != 0 || strcmp(label, "temp"))
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continue;
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memset(buf, 0, sizeof(buf));
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if (!gsc_i2c_read(priv->hwmon, reg, buf, sizeof(buf))) {
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val = buf[0] | buf[1] << 8;
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if (val > 0x8000)
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val -= 0xffff;
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return val;
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}
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}
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return 0;
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}
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static void gsc_thermal_info(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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switch (priv->gscver) {
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case 2:
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printf("board_temp:%dC ", gsc_thermal_get_temp(dev) / 10);
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break;
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case 3:
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if (priv->fwver > 52) {
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bool enabled;
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int tmax;
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if (!gsc_thermal_get_info(dev, NULL, &tmax, &enabled)) {
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puts("Thermal protection:");
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if (enabled)
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printf("enabled at %dC ", tmax);
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else
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puts("disabled ");
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}
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}
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break;
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}
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}
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static void gsc_reset_info(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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static const char * const names[] = {
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"VIN",
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"PB",
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"WDT",
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"CPU",
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"TEMP_L",
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"TEMP_R",
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"SLEEP",
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"BOOT_WDT1",
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"BOOT_WDT2",
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"SOFT_PWR",
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};
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u8 reg;
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/* reset cause */
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switch (priv->gscver) {
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case 2:
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if (!gsc_i2c_read(dev, GSC_SC_STATUS, ®, 1)) {
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if (reg & BIT(GSC_SC_IRQ_WATCHDOG)) {
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puts("RST:WDT");
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reg &= ~BIT(GSC_SC_IRQ_WATCHDOG);
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gsc_i2c_write(dev, GSC_SC_STATUS, ®, 1);
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} else {
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puts("RST:VIN");
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}
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printf(" WDT:%sabled ",
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(reg & BIT(GSC_SC_CTRL1_WDEN)) ? "en" : "dis");
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}
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break;
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case 3:
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if (priv->fwver > 52 &&
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!gsc_i2c_read(dev, GSC_SC_RST_CAUSE, ®, 1)) {
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puts("RST:");
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if (reg < ARRAY_SIZE(names))
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printf("%s ", names[reg]);
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else
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printf("0x%02x ", reg);
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}
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break;
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}
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}
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/* display hardware monitor ADC channels */
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static int gsc_hwmon(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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u32 reg, mode, val, offset;
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const char *label;
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ofnode node;
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u8 buf[2];
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u32 r[2];
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int ret;
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/* iterate over hwmon nodes */
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ofnode_for_each_subnode(node, dev_read_subnode(dev, "adc")) {
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if (ofnode_read_u32(node, "reg", ®))
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reg = -1;
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if (ofnode_read_u32(node, "gw,mode", &mode))
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mode = -1;
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label = ofnode_read_string(node, "label");
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if ((reg == -1) || (mode == -1) || !label)
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continue;
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memset(buf, 0, sizeof(buf));
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ret = gsc_i2c_read(priv->hwmon, reg, buf, sizeof(buf));
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if (ret) {
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printf("i2c error: %d\n", ret);
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continue;
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}
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val = buf[0] | buf[1] << 8;
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switch (mode) {
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case 0: /* temperature (C*10) */
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if (val > 0x8000)
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val -= 0xffff;
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printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
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break;
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case 1: /* prescaled voltage */
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if (val != 0xffff)
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printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
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break;
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case 2: /* scaled based on ref volt and resolution */
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val *= 2500;
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val /= 1 << 12;
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/* apply pre-scaler voltage divider */
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if (!ofnode_read_u32_index(node, "gw,voltage-divider-ohms", 0, &r[0]) &&
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!ofnode_read_u32_index(node, "gw,voltage-divider-ohms", 1, &r[1]) &&
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r[0] && r[1]) {
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val *= (r[0] + r[1]);
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val /= r[1];
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}
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/* adjust by offset */
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val += (offset / 1000);
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printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
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break;
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}
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}
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return 0;
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}
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static int gsc_banner(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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/* banner */
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printf("GSCv%d : v%d 0x%04x ", priv->gscver, priv->fwver, priv->fwcrc);
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gsc_reset_info(dev);
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gsc_thermal_info(dev);
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puts("\n");
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/* Display RTC */
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if (priv->rtc) {
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u8 buf[4];
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time_t timestamp;
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struct rtc_time tm;
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if (!gsc_i2c_read(priv->rtc, 0, buf, 4)) {
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timestamp = get_unaligned_le32(buf);
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rtc_to_tm(timestamp, &tm);
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printf("RTC : %4d-%02d-%02d %2d:%02d:%02d UTC\n",
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tm.tm_year, tm.tm_mon, tm.tm_mday,
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tm.tm_hour, tm.tm_min, tm.tm_sec);
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}
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}
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return 0;
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}
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static int gsc_probe(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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u8 buf[32];
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int ret;
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ret = gsc_i2c_read(dev, 0, buf, sizeof(buf));
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if (ret)
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return ret;
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/*
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* GSC chip version:
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* GSCv2 has 16 registers (which overlap)
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* GSCv3 has 32 registers
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*/
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priv->gscver = memcmp(buf, buf + 16, 16) ? 3 : 2;
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priv->fwver = buf[GSC_SC_FWVER];
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priv->fwcrc = buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8;
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priv->hwmon = gsc_get_dev(GSC_BUSNO, GSC_HWMON_ADDR);
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if (priv->hwmon)
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dev_set_priv(priv->hwmon, priv);
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priv->rtc = gsc_get_dev(GSC_BUSNO, GSC_RTC_ADDR);
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if (priv->rtc)
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dev_set_priv(priv->rtc, priv);
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#ifdef CONFIG_SPL_BUILD
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gsc_banner(dev);
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#endif
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return 0;
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};
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static const struct udevice_id gsc_ids[] = {
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{ .compatible = "gw,gsc", },
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{ }
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};
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U_BOOT_DRIVER(gsc) = {
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.name = "gsc",
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.id = UCLASS_MISC,
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.of_match = gsc_ids,
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.probe = gsc_probe,
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.priv_auto = sizeof(struct gsc_priv),
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.flags = DM_FLAG_PRE_RELOC,
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};
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static int gsc_sleep(struct udevice *dev, unsigned long secs)
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{
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u8 regs[4];
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int ret;
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printf("GSC Sleeping for %ld seconds\n", secs);
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put_unaligned_le32(secs, regs);
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ret = gsc_i2c_write(dev, GSC_SC_TIME_ADD, regs, sizeof(regs));
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if (ret)
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goto err;
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ret = gsc_i2c_read(dev, GSC_SC_CTRL1, regs, 1);
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if (ret)
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goto err;
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regs[0] |= BIT(GSC_SC_CTRL1_SLEEP_ADD);
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ret = gsc_i2c_write(dev, GSC_SC_CTRL1, regs, 1);
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if (ret)
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goto err;
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regs[0] &= ~BIT(GSC_SC_CTRL1_SLEEP_ADD);
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regs[0] |= BIT(GSC_SC_CTRL1_SLEEP_EN) | BIT(GSC_SC_CTRL1_SLEEP_ACTIVATE);
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ret = gsc_i2c_write(dev, GSC_SC_CTRL1, regs, 1);
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if (ret)
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goto err;
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return 0;
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err:
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printf("i2c error: %d\n", ret);
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return ret;
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}
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static int gsc_wd_disable(struct udevice *dev)
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{
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int ret;
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u8 reg;
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ret = gsc_i2c_read(dev, GSC_SC_CTRL1, ®, 1);
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if (ret)
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goto err;
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reg |= BIT(GSC_SC_CTRL1_WDDIS);
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reg &= ~BIT(GSC_SC_CTRL1_BOOT_CHK);
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ret = gsc_i2c_write(dev, GSC_SC_CTRL1, ®, 1);
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if (ret)
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goto err;
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puts("GSC : boot watchdog disabled\n");
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return 0;
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err:
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puts("i2c error");
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return ret;
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}
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static int gsc_thermal(struct udevice *dev, const char *cmd, const char *val)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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int ret, tmax;
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bool enabled;
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u8 reg;
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if (priv->gscver < 3 || priv->fwver < 53)
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return -EINVAL;
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ret = gsc_thermal_get_info(dev, ®, &tmax, &enabled);
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if (ret)
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return ret;
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if (cmd && !strcmp(cmd, "enable")) {
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if (val && *val) {
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tmax = clamp((int)simple_strtoul(val, NULL, 0), 72, 122);
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reg &= ~0xf8;
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reg |= ((tmax - 70) / 2) << 3;
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}
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reg |= BIT(0);
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gsc_i2c_write(dev, GSC_SC_THERM_PROTECT, ®, 1);
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} else if (cmd && !strcmp(cmd, "disable")) {
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reg &= ~BIT(0);
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gsc_i2c_write(dev, GSC_SC_THERM_PROTECT, ®, 1);
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} else if (cmd) {
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return -EINVAL;
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}
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/* show status */
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gsc_thermal_info(dev);
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puts("\n");
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return 0;
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}
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/* override in board files to display additional board EEPROM info */
|
|
__weak void board_gsc_info(void)
|
|
{
|
|
}
|
|
|
|
static void gsc_info(struct udevice *dev)
|
|
{
|
|
gsc_banner(dev);
|
|
board_gsc_info();
|
|
}
|
|
|
|
static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
/* get/probe driver */
|
|
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev);
|
|
if (ret)
|
|
return CMD_RET_USAGE;
|
|
if (argc < 2) {
|
|
gsc_info(dev);
|
|
return CMD_RET_SUCCESS;
|
|
} else if (strcasecmp(argv[1], "sleep") == 0) {
|
|
if (argc < 3)
|
|
return CMD_RET_USAGE;
|
|
if (!gsc_sleep(dev, dectoul(argv[2], NULL)))
|
|
return CMD_RET_SUCCESS;
|
|
} else if (strcasecmp(argv[1], "hwmon") == 0) {
|
|
if (!gsc_hwmon(dev))
|
|
return CMD_RET_SUCCESS;
|
|
} else if (strcasecmp(argv[1], "wd-disable") == 0) {
|
|
if (!gsc_wd_disable(dev))
|
|
return CMD_RET_SUCCESS;
|
|
} else if (strcasecmp(argv[1], "thermal") == 0) {
|
|
char *cmd, *val;
|
|
|
|
cmd = (argc > 2) ? argv[2] : NULL;
|
|
val = (argc > 3) ? argv[3] : NULL;
|
|
if (!gsc_thermal(dev, cmd, val))
|
|
return CMD_RET_SUCCESS;
|
|
}
|
|
|
|
return CMD_RET_USAGE;
|
|
}
|
|
|
|
U_BOOT_CMD(gsc, 4, 1, do_gsc, "Gateworks System Controller",
|
|
"[sleep <secs>]|[hwmon]|[wd-disable][thermal [disable|enable [temp]]]\n");
|
|
|
|
/* disable boot watchdog - useful for an SPL that wants to use falcon mode */
|
|
int gsc_boot_wd_disable(void)
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
/* get/probe driver */
|
|
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev);
|
|
if (!ret)
|
|
ret = gsc_wd_disable(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
# else
|
|
|
|
/*
|
|
* GSCv2 will fail to ACK an I2C transaction if it is busy, which can occur
|
|
* during its 1HZ timer tick while reading ADC's. When this does occur,
|
|
* it will never be busy longer than 2 back-to-back transfers so retry 3 times.
|
|
*/
|
|
static int gsc_i2c_read(uint chip, uint addr, u8 *buf, int len)
|
|
{
|
|
int retry = 3;
|
|
int n = 0;
|
|
int ret;
|
|
|
|
while (n++ < retry) {
|
|
ret = i2c_read(chip, addr, 1, buf, len);
|
|
if (!ret)
|
|
break;
|
|
if (ret != -EREMOTEIO)
|
|
break;
|
|
printf("%s 0x%02x retry %d\n", __func__, addr, n);
|
|
mdelay(10);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int gsc_i2c_write(uint chip, uint addr, u8 *buf, int len)
|
|
{
|
|
int retry = 3;
|
|
int n = 0;
|
|
int ret;
|
|
|
|
while (n++ < retry) {
|
|
ret = i2c_write(chip, addr, 1, buf, len);
|
|
if (!ret)
|
|
break;
|
|
if (ret != -EREMOTEIO)
|
|
break;
|
|
printf("%s 0x%02x retry %d\n", __func__, addr, n);
|
|
mdelay(10);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/* disable boot watchdog - useful for an SPL that wants to use falcon mode */
|
|
int gsc_boot_wd_disable(void)
|
|
{
|
|
u8 buf[32];
|
|
int ret;
|
|
|
|
i2c_set_bus_num(GSC_BUSNO);
|
|
ret = gsc_i2c_read(GSC_SC_ADDR, 0, buf, sizeof(buf));
|
|
if (!ret) {
|
|
buf[GSC_SC_CTRL1] |= BIT(GSC_SC_CTRL1_WDDIS);
|
|
ret = gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, &buf[GSC_SC_CTRL1], 1);
|
|
printf("GSCv%d: v%d 0x%04x ",
|
|
memcmp(buf, buf + 16, 16) ? 3 : 2,
|
|
buf[GSC_SC_FWVER],
|
|
buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8);
|
|
if (buf[GSC_SC_STATUS] & BIT(GSC_SC_IRQ_WATCHDOG)) {
|
|
puts("RST:WDT ");
|
|
buf[GSC_SC_STATUS] &= ~BIT(GSC_SC_IRQ_WATCHDOG);
|
|
gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, &buf[GSC_SC_STATUS], 1);
|
|
} else {
|
|
puts("RST:VIN ");
|
|
}
|
|
puts("WDT:disabled\n");
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#endif
|