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https://github.com/AsahiLinux/u-boot
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2132fce7e1
This patch add support for using NXP's pca8574 I2C IO expander, which has only 8 IO lines. After this change the .data member's information from struct udevice_id are used to either sent one or two bytes. Moreover, the '_le16' suffix from pcf8575_i2c_{write|read}_le16() functions have been removed as now we also sent 8 bit data. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
177 lines
4.4 KiB
C
177 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCF8575 I2C GPIO EXPANDER DRIVER
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*
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Vignesh R <vigneshr@ti.com>
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*
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*
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* Driver for TI PCF-8575 16-bit I2C gpio expander. Based on
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* gpio-pcf857x Linux Kernel(v4.7) driver.
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*
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* Copyright (C) 2007 David Brownell
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*
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* Add support for 8 bit expanders - like pca8574
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* Copyright (C) 2021 Lukasz Majewski - DENX Software Engineering
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <i2c.h>
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#include <log.h>
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#include <asm-generic/gpio.h>
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#include <asm/global_data.h>
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct pcf8575_chip {
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/* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
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* We can't actually know whether a pin is configured (a) as output
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* and driving the signal low, or (b) as input and reporting a low
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* value ... without knowing the last value written since the chip
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* came out of reset (if any). We can't read the latched output.
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* In short, the only reliable solution for setting up pin direction
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* is to do it explicitly.
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*
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* Using "out" avoids that trouble. When left initialized to zero,
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* our software copy of the "latch" then matches the chip's all-ones
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* reset state. Otherwise it flags pins to be driven low.
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*/
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unsigned int out; /* software latch */
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};
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/* Read/Write to I/O expander */
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static int pcf8575_i2c_write(struct udevice *dev, unsigned int word)
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{
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struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
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u8 buf[2] = { word & 0xff, word >> 8, };
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int ret;
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ret = dm_i2c_write(dev, 0, buf, dev_get_driver_data(dev));
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if (ret)
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printf("%s i2c write failed to addr %x\n", __func__,
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chip->chip_addr);
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return ret;
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}
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static int pcf8575_i2c_read(struct udevice *dev)
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{
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struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
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u8 buf[2] = {0x00, 0x00};
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int ret;
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ret = dm_i2c_read(dev, 0, buf, dev_get_driver_data(dev));
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if (ret) {
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printf("%s i2c read failed from addr %x\n", __func__,
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chip->chip_addr);
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return ret;
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}
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return (buf[1] << 8) | buf[0];
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}
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static int pcf8575_direction_input(struct udevice *dev, unsigned offset)
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{
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struct pcf8575_chip *plat = dev_get_plat(dev);
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int status;
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plat->out |= BIT(offset);
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status = pcf8575_i2c_write(dev, plat->out);
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return status;
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}
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static int pcf8575_direction_output(struct udevice *dev,
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unsigned int offset, int value)
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{
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struct pcf8575_chip *plat = dev_get_plat(dev);
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int ret;
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if (value)
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plat->out |= BIT(offset);
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else
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plat->out &= ~BIT(offset);
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ret = pcf8575_i2c_write(dev, plat->out);
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return ret;
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}
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static int pcf8575_get_value(struct udevice *dev, unsigned int offset)
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{
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int value;
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value = pcf8575_i2c_read(dev);
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return (value < 0) ? value : ((value & BIT(offset)) >> offset);
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}
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static int pcf8575_set_value(struct udevice *dev, unsigned int offset,
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int value)
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{
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return pcf8575_direction_output(dev, offset, value);
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}
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static int pcf8575_ofdata_plat(struct udevice *dev)
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{
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struct pcf8575_chip *plat = dev_get_plat(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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int n_latch;
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/*
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* Number of pins depends on the expander device and is specified
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* in the struct udevice_id (as in the Linue kernel).
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*/
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uc_priv->gpio_count = dev_get_driver_data(dev) * 8;
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uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
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"gpio-bank-name", NULL);
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if (!uc_priv->bank_name)
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uc_priv->bank_name = fdt_get_name(gd->fdt_blob,
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dev_of_offset(dev), NULL);
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n_latch = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
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"lines-initial-states", 0);
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plat->out = ~n_latch;
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return 0;
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}
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static int pcf8575_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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debug("%s GPIO controller with %d gpios probed\n",
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uc_priv->bank_name, uc_priv->gpio_count);
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return 0;
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}
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static const struct dm_gpio_ops pcf8575_gpio_ops = {
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.direction_input = pcf8575_direction_input,
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.direction_output = pcf8575_direction_output,
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.get_value = pcf8575_get_value,
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.set_value = pcf8575_set_value,
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};
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static const struct udevice_id pcf8575_gpio_ids[] = {
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{ .compatible = "nxp,pcf8575", .data = 2 },
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{ .compatible = "ti,pcf8575", .data = 2 },
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{ .compatible = "nxp,pca8574", .data = 1 },
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{ }
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};
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U_BOOT_DRIVER(gpio_pcf8575) = {
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.name = "gpio_pcf8575",
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.id = UCLASS_GPIO,
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.ops = &pcf8575_gpio_ops,
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.of_match = pcf8575_gpio_ids,
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.of_to_plat = pcf8575_ofdata_plat,
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.probe = pcf8575_gpio_probe,
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.plat_auto = sizeof(struct pcf8575_chip),
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};
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