mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
169 lines
4.4 KiB
C
169 lines
4.4 KiB
C
/*
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* Synopsys HSDK SDP Generic PLL clock driver
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*
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* Copyright (C) 2017 Synopsys
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* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <log.h>
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#include <asm-generic/gpio.h>
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#include <asm/io.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <linux/bitops.h>
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#include <linux/printk.h>
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#define DRV_NAME "gpio_creg"
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struct hsdk_creg_gpio {
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u32 *regs;
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u8 shift;
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u8 activate;
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u8 deactivate;
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u8 bit_per_gpio;
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};
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static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
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{
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struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
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u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift;
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u32 reg = readl(hcg->regs);
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reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift);
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reg |= ((val ? hcg->deactivate : hcg->activate) << reg_shift);
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writel(reg, hcg->regs);
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return 0;
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}
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static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft,
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int val)
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{
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hsdk_creg_gpio_set_value(dev, oft, val);
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return 0;
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}
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static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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pr_err("%s can't be used as input!\n", uc_priv->bank_name);
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return -ENOTSUPP;
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}
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static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
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{
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struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
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u32 val = readl(hcg->regs);
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val >>= oft * hcg->bit_per_gpio + hcg->shift;
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val &= GENMASK(hcg->bit_per_gpio - 1, 0);
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return (val == hcg->deactivate) ? 1 : 0;
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}
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static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
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.direction_output = hsdk_creg_gpio_direction_output,
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.direction_input = hsdk_creg_gpio_direction_input,
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.set_value = hsdk_creg_gpio_set_value,
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.get_value = hsdk_creg_gpio_get_value,
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};
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static int hsdk_creg_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
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u32 shift, bit_per_gpio, activate, deactivate, gpio_count;
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const u8 *defaults;
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hcg->regs = dev_read_addr_ptr(dev);
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gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
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shift = dev_read_u32_default(dev, "gpio-first-shift", 0);
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bit_per_gpio = dev_read_u32_default(dev, "gpio-bit-per-line", 1);
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activate = dev_read_u32_default(dev, "gpio-activate-val", 1);
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deactivate = dev_read_u32_default(dev, "gpio-deactivate-val", 0);
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defaults = dev_read_u8_array_ptr(dev, "gpio-default-val", gpio_count);
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uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
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if (!uc_priv->bank_name)
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uc_priv->bank_name = dev_read_name(dev);
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if (!bit_per_gpio) {
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pr_err("%s: 'gpio-bit-per-line' can't be 0\n",
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uc_priv->bank_name);
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return -EINVAL;
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}
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if (!gpio_count) {
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pr_err("%s: 'gpio-count' can't be 0\n",
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uc_priv->bank_name);
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return -EINVAL;
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}
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if ((gpio_count * bit_per_gpio + shift) > 32) {
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pr_err("%s: u32 io register overflow: try to use %u bits\n",
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uc_priv->bank_name, gpio_count * bit_per_gpio + shift);
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return -EINVAL;
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}
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if (GENMASK(31, bit_per_gpio) & activate) {
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pr_err("%s: 'gpio-activate-val' can't be more than %lu\n",
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uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));
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return -EINVAL;
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}
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if (GENMASK(31, bit_per_gpio) & deactivate) {
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pr_err("%s: 'gpio-deactivate-val' can't be more than %lu\n",
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uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));
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return -EINVAL;
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}
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if (activate == deactivate) {
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pr_err("%s: 'gpio-deactivate-val' and 'gpio-activate-val' can't be equal\n",
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uc_priv->bank_name);
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return -EINVAL;
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}
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hcg->shift = (u8)shift;
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hcg->bit_per_gpio = (u8)bit_per_gpio;
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hcg->activate = (u8)activate;
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hcg->deactivate = (u8)deactivate;
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uc_priv->gpio_count = gpio_count;
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/* Setup default GPIO value if we have "gpio-default-val" array */
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if (defaults)
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for (u8 i = 0; i < gpio_count; i++)
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hsdk_creg_gpio_set_value(dev, i, defaults[i]);
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pr_debug("%s GPIO [0x%p] controller with %d gpios probed\n",
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uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);
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return 0;
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}
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static const struct udevice_id hsdk_creg_gpio_ids[] = {
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{ .compatible = "snps,creg-gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_hsdk_creg) = {
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.name = DRV_NAME,
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.id = UCLASS_GPIO,
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.ops = &hsdk_creg_gpio_ops,
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.probe = hsdk_creg_gpio_probe,
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.of_match = hsdk_creg_gpio_ids,
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.plat_auto = sizeof(struct hsdk_creg_gpio),
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};
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