mirror of
https://github.com/AsahiLinux/u-boot
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29caf9305b
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
427 lines
9.6 KiB
C
427 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Intel Corporation <www.intel.com>
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*/
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#include <common.h>
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#include <altera.h>
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#include <log.h>
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#include <watchdog.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/smc_api.h>
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#include <linux/delay.h>
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#include <linux/intel-smc.h>
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#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
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#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
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#define BITSTREAM_CHUNK_SIZE 0xFFFF0
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#define RECONFIG_STATUS_POLL_RETRY_MAX 100
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/*
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* Polling the FPGA configuration status.
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* Return 0 for success, non-zero for error.
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*/
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static int reconfig_status_polling_resp(void)
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{
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int ret;
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unsigned long start = get_timer(0);
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while (1) {
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ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
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NULL, 0);
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if (!ret)
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return 0; /* configuration success */
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if (ret != INTEL_SIP_SMC_STATUS_BUSY)
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return ret;
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if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
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return -ETIMEDOUT; /* time out */
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puts(".");
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udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
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schedule();
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}
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return -ETIMEDOUT;
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}
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static int send_bitstream(const void *rbf_data, size_t rbf_size)
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{
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int i;
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u64 res_buf[3];
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u64 args[2];
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u32 xfer_count = 0;
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int ret, wr_ret = 0, retry = 0;
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size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
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BITSTREAM_CHUNK_SIZE : rbf_size;
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while (rbf_size || xfer_count) {
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if (!wr_ret && rbf_size) {
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args[0] = (u64)rbf_data;
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args[1] = buf_size;
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wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
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args, 2, NULL, 0);
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debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
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wr_ret, rbf_data, buf_size);
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if (wr_ret)
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continue;
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rbf_size -= buf_size;
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rbf_data += buf_size;
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if (buf_size >= rbf_size)
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buf_size = rbf_size;
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xfer_count++;
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puts(".");
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} else {
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ret = invoke_smc(
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INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
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NULL, 0, res_buf, ARRAY_SIZE(res_buf));
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if (!ret) {
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for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
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if (!res_buf[i])
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break;
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xfer_count--;
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wr_ret = 0;
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retry = 0;
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}
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} else if (ret !=
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INTEL_SIP_SMC_STATUS_BUSY)
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return ret;
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else if (!xfer_count)
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return INTEL_SIP_SMC_STATUS_ERROR;
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if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
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return -ETIMEDOUT;
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udelay(20000);
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}
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schedule();
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}
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return 0;
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}
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/*
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* This is the interface used by FPGA driver.
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* Return 0 for success, non-zero for error.
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*/
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int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
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{
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int ret;
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u64 arg = 1;
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debug("Invoking FPGA_CONFIG_START...\n");
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ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
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if (ret) {
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puts("Failure in RECONFIG mailbox command!\n");
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return ret;
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}
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ret = send_bitstream(rbf_data, rbf_size);
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if (ret) {
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puts("Error sending bitstream!\n");
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return ret;
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}
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/* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
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udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
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debug("Polling with MBOX_RECONFIG_STATUS...\n");
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ret = reconfig_status_polling_resp();
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if (ret) {
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puts("FPGA reconfiguration failed!");
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return ret;
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}
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puts("FPGA reconfiguration OK!\n");
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return ret;
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}
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#else
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static const struct mbox_cfgstat_state {
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int err_no;
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const char *error_name;
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} mbox_cfgstat_state[] = {
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{MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."},
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{MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."},
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{MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"},
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{MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"},
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{MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"},
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{MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"},
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{MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"},
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{MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"},
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{MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"},
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{MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"},
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{MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"},
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{MBOX_RESP_ERROR, "Mailbox general error!"},
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{-ETIMEDOUT, "I/O timeout error"},
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{-1, "Unknown error!"}
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};
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#define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state)
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static const char *mbox_cfgstat_to_str(int err)
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{
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int i;
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for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) {
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if (mbox_cfgstat_state[i].err_no == err)
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return mbox_cfgstat_state[i].error_name;
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}
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return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name;
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}
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/*
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* Add the ongoing transaction's command ID into pending list and return
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* the command ID for next transfer.
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*/
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static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id)
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{
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int i;
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for (i = 0; i < list_size; i++) {
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if (xfer_pending_list[i])
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continue;
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xfer_pending_list[i] = id;
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debug("ID(%d) added to transaction pending list\n", id);
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/*
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* Increment command ID for next transaction.
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* Valid command ID (4 bits) is from 1 to 15.
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*/
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id = (id % 15) + 1;
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break;
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}
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return id;
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}
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/*
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* Check whether response ID match the command ID in the transfer
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* pending list. If a match is found in the transfer pending list,
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* it clears the transfer pending list and return the matched
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* command ID.
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*/
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static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size,
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u8 id)
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{
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int i;
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for (i = 0; i < list_size; i++) {
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if (id != xfer_pending_list[i])
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continue;
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xfer_pending_list[i] = 0;
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return id;
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}
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return 0;
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}
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/*
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* Polling the FPGA configuration status.
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* Return 0 for success, non-zero for error.
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*/
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static int reconfig_status_polling_resp(void)
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{
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int ret;
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unsigned long start = get_timer(0);
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while (1) {
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ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
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if (!ret)
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return 0; /* configuration success */
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if (ret != MBOX_CFGSTAT_STATE_CONFIG)
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return ret;
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if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
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break; /* time out */
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puts(".");
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udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
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schedule();
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}
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return -ETIMEDOUT;
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}
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static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count,
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u32 *resp_buf, u32 buf_size, u32 client_id)
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{
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u32 buf[MBOX_RESP_BUFFER_SIZE];
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u32 mbox_hdr;
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u32 resp_len;
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u32 hdr_len;
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u32 i;
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if (*resp_count < buf_size) {
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u32 rcv_len_max = buf_size - *resp_count;
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if (rcv_len_max > MBOX_RESP_BUFFER_SIZE)
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rcv_len_max = MBOX_RESP_BUFFER_SIZE;
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resp_len = mbox_rcv_resp(buf, rcv_len_max);
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for (i = 0; i < resp_len; i++) {
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resp_buf[(*w_index)++] = buf[i];
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*w_index %= buf_size;
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(*resp_count)++;
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}
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}
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/* No response in buffer */
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if (*resp_count == 0)
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return 0;
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mbox_hdr = resp_buf[*r_index];
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hdr_len = MBOX_RESP_LEN_GET(mbox_hdr);
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/* Insufficient header length to return a mailbox header */
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if ((*resp_count - 1) < hdr_len)
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return 0;
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*r_index += (hdr_len + 1);
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*r_index %= buf_size;
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*resp_count -= (hdr_len + 1);
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/* Make sure response belongs to us */
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if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id)
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return 0;
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return mbox_hdr;
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}
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/* Send bit stream data to SDM via RECONFIG_DATA mailbox command */
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static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
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u32 xfer_max, u32 buf_size_max)
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{
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u32 response_buffer[MBOX_RESP_BUFFER_SIZE];
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u32 xfer_pending[MBOX_RESP_BUFFER_SIZE];
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u32 resp_rindex = 0;
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u32 resp_windex = 0;
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u32 resp_count = 0;
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u32 xfer_count = 0;
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int resp_err = 0;
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u8 cmd_id = 1;
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u32 args[3];
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int ret;
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debug("SDM xfer_max = %d\n", xfer_max);
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debug("SDM buf_size_max = %x\n\n", buf_size_max);
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memset(xfer_pending, 0, sizeof(xfer_pending));
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while (rbf_size || xfer_count) {
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if (!resp_err && rbf_size && xfer_count < xfer_max) {
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args[0] = MBOX_ARG_DESC_COUNT(1);
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args[1] = (u64)rbf_data;
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if (rbf_size >= buf_size_max) {
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args[2] = buf_size_max;
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rbf_size -= buf_size_max;
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rbf_data += buf_size_max;
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} else {
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args[2] = (u64)rbf_size;
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rbf_size = 0;
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}
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resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
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MBOX_CMD_INDIRECT, 3, args);
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if (!resp_err) {
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xfer_count++;
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cmd_id = add_transfer(xfer_pending,
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MBOX_RESP_BUFFER_SIZE,
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cmd_id);
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}
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puts(".");
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} else {
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u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex,
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&resp_count,
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response_buffer,
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MBOX_RESP_BUFFER_SIZE,
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MBOX_CLIENT_ID_UBOOT);
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/*
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* If no valid response header found or
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* non-zero length from RECONFIG_DATA
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*/
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if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr))
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continue;
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/* Check for response's status */
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if (!resp_err) {
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resp_err = MBOX_RESP_ERR_GET(resp_hdr);
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debug("Response error code: %08x\n", resp_err);
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}
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ret = get_and_clr_transfer(xfer_pending,
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MBOX_RESP_BUFFER_SIZE,
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MBOX_RESP_ID_GET(resp_hdr));
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if (ret) {
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/* Claim and reuse the ID */
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cmd_id = (u8)ret;
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xfer_count--;
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}
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if (resp_err && !xfer_count)
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return resp_err;
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}
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schedule();
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}
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return 0;
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}
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/*
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* This is the interface used by FPGA driver.
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* Return 0 for success, non-zero for error.
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*/
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int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
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{
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int ret;
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u32 resp_len = 2;
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u32 resp_buf[2];
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debug("Sending MBOX_RECONFIG...\n");
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ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
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NULL, 0, &resp_len, resp_buf);
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if (ret) {
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puts("Failure in RECONFIG mailbox command!\n");
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return ret;
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}
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ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]);
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if (ret) {
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printf("RECONFIG_DATA error: %08x, %s\n", ret,
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mbox_cfgstat_to_str(ret));
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return ret;
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}
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/* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
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udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
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debug("Polling with MBOX_RECONFIG_STATUS...\n");
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ret = reconfig_status_polling_resp();
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if (ret) {
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printf("RECONFIG_STATUS Error: %08x, %s\n", ret,
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mbox_cfgstat_to_str(ret));
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return ret;
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}
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puts("FPGA reconfiguration OK!\n");
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return ret;
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}
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#endif
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