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17bae7766c
Add support of offset and linear calibration for STM32MP15. The calibration is performed once at probe. The ADC is set in power on state for calibration. It remains in this state after calibration, to give to the kernel the opportunity to retrieve calibration data, directly from the ADC. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
423 lines
11 KiB
C
423 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>
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*
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* Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc.c.
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*/
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#include <common.h>
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#include <adc.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "stm32-adc-core.h"
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/* STM32H7 - Registers for each ADC instance */
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#define STM32H7_ADC_ISR 0x00
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#define STM32H7_ADC_CR 0x08
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#define STM32H7_ADC_CFGR 0x0C
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#define STM32H7_ADC_SMPR1 0x14
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#define STM32H7_ADC_SMPR2 0x18
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#define STM32H7_ADC_PCSEL 0x1C
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#define STM32H7_ADC_SQR1 0x30
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#define STM32H7_ADC_DR 0x40
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#define STM32H7_ADC_DIFSEL 0xC0
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/* STM32H7_ADC_ISR - bit fields */
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#define STM32MP1_VREGREADY BIT(12)
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#define STM32H7_EOC BIT(2)
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#define STM32H7_ADRDY BIT(0)
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/* STM32H7_ADC_CR - bit fields */
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#define STM32H7_ADCAL BIT(31)
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#define STM32H7_ADCALDIF BIT(30)
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#define STM32H7_DEEPPWD BIT(29)
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#define STM32H7_ADVREGEN BIT(28)
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#define STM32H7_ADCALLIN BIT(16)
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#define STM32H7_BOOST BIT(8)
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#define STM32H7_ADSTART BIT(2)
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#define STM32H7_ADDIS BIT(1)
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#define STM32H7_ADEN BIT(0)
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/* STM32H7_ADC_CFGR bit fields */
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#define STM32H7_EXTEN GENMASK(11, 10)
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#define STM32H7_DMNGT GENMASK(1, 0)
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/* STM32H7_ADC_SQR1 - bit fields */
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#define STM32H7_SQ1_SHIFT 6
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/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
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#define STM32H7_BOOST_CLKRATE 20000000UL
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#define STM32_ADC_CH_MAX 20 /* max number of channels */
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#define STM32_ADC_TIMEOUT_US 100000
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struct stm32_adc_cfg {
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unsigned int max_channels;
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unsigned int num_bits;
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bool has_vregready;
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};
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struct stm32_adc {
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void __iomem *regs;
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int active_channel;
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const struct stm32_adc_cfg *cfg;
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};
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static void stm32_adc_enter_pwr_down(struct udevice *dev)
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{
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struct stm32_adc *adc = dev_get_priv(dev);
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clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
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/* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
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}
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static int stm32_adc_exit_pwr_down(struct udevice *dev)
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{
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struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
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struct stm32_adc *adc = dev_get_priv(dev);
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int ret;
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u32 val;
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/* return immediately if ADC is not in deep power down mode */
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if (!(readl(adc->regs + STM32H7_ADC_CR) & STM32H7_DEEPPWD))
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return 0;
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/* Exit deep power down, then enable ADC voltage regulator */
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clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADVREGEN);
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if (common->rate > STM32H7_BOOST_CLKRATE)
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
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/* Wait for startup time */
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if (!adc->cfg->has_vregready) {
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udelay(20);
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return 0;
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}
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ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
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val & STM32MP1_VREGREADY,
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STM32_ADC_TIMEOUT_US);
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if (ret < 0) {
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stm32_adc_enter_pwr_down(dev);
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dev_err(dev, "Failed to enable vreg: %d\n", ret);
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}
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return ret;
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}
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static int stm32_adc_stop(struct udevice *dev)
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{
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struct stm32_adc *adc = dev_get_priv(dev);
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADDIS);
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stm32_adc_enter_pwr_down(dev);
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adc->active_channel = -1;
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return 0;
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}
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static int stm32_adc_start_channel(struct udevice *dev, int channel)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct stm32_adc *adc = dev_get_priv(dev);
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int ret;
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u32 val;
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ret = stm32_adc_exit_pwr_down(dev);
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if (ret < 0)
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return ret;
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/* Only use single ended channels */
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writel(0, adc->regs + STM32H7_ADC_DIFSEL);
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/* Enable ADC, Poll for ADRDY to be set (after adc startup time) */
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADEN);
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ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
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val & STM32H7_ADRDY, STM32_ADC_TIMEOUT_US);
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if (ret < 0) {
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stm32_adc_stop(dev);
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dev_err(dev, "Failed to enable ADC: %d\n", ret);
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return ret;
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}
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/* Preselect channels */
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writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL);
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/* Set sampling time to max value by default */
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writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR1);
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writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR2);
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/* Program regular sequence: chan in SQ1 & len = 0 for one channel */
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writel(channel << STM32H7_SQ1_SHIFT, adc->regs + STM32H7_ADC_SQR1);
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/* Trigger detection disabled (conversion can be launched in SW) */
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clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN |
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STM32H7_DMNGT);
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adc->active_channel = channel;
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return 0;
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}
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static int stm32_adc_channel_data(struct udevice *dev, int channel,
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unsigned int *data)
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{
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struct stm32_adc *adc = dev_get_priv(dev);
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int ret;
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u32 val;
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if (channel != adc->active_channel) {
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dev_err(dev, "Requested channel is not active!\n");
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return -EINVAL;
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}
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADSTART);
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ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
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val & STM32H7_EOC, STM32_ADC_TIMEOUT_US);
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if (ret < 0) {
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dev_err(dev, "conversion timed out: %d\n", ret);
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return ret;
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}
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*data = readl(adc->regs + STM32H7_ADC_DR);
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return 0;
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}
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/**
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* Fixed timeout value for ADC calibration.
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* worst cases:
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* - low clock frequency (0.12 MHz min)
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* - maximum prescalers
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* Calibration requires:
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* - 16384 ADC clock cycle for the linear calibration
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* - 20 ADC clock cycle for the offset calibration
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*
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* Set to 100ms for now
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*/
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#define STM32H7_ADC_CALIB_TIMEOUT_US 100000
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static int stm32_adc_selfcalib(struct udevice *dev)
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{
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struct stm32_adc *adc = dev_get_priv(dev);
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int ret;
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u32 val;
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/*
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* Select calibration mode:
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* - Offset calibration for single ended inputs
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* - No linearity calibration. Done in next step.
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*/
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clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADCALDIF | STM32H7_ADCALLIN);
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/* Start calibration, then wait for completion */
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADCAL);
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ret = readl_poll_sleep_timeout(adc->regs + STM32H7_ADC_CR, val,
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!(val & STM32H7_ADCAL), 100,
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STM32H7_ADC_CALIB_TIMEOUT_US);
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if (ret) {
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dev_err(dev, "calibration failed\n");
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goto out;
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}
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/*
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* Select calibration mode, then start calibration:
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* - Offset calibration for differential input
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* - Linearity calibration (needs to be done only once for single/diff)
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* will run simultaneously with offset calibration.
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*/
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADCALDIF | STM32H7_ADCALLIN);
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/* Start calibration, then wait for completion */
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADCAL);
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ret = readl_poll_sleep_timeout(adc->regs + STM32H7_ADC_CR, val,
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!(val & STM32H7_ADCAL), 100,
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STM32H7_ADC_CALIB_TIMEOUT_US);
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if (ret)
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dev_err(dev, "calibration failed\n");
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out:
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clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADCALDIF | STM32H7_ADCALLIN);
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return ret;
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}
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static int stm32_adc_get_legacy_chan_count(struct udevice *dev)
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{
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int ret;
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/* Retrieve single ended channels listed in device tree */
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ret = dev_read_size(dev, "st,adc-channels");
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if (ret < 0) {
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dev_err(dev, "can't get st,adc-channels: %d\n", ret);
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return ret;
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}
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return (ret / sizeof(u32));
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}
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static int stm32_adc_legacy_chan_init(struct udevice *dev, unsigned int num_channels)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct stm32_adc *adc = dev_get_priv(dev);
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u32 chans[STM32_ADC_CH_MAX];
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int i, ret;
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ret = dev_read_u32_array(dev, "st,adc-channels", chans, num_channels);
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if (ret < 0) {
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dev_err(dev, "can't read st,adc-channels: %d\n", ret);
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return ret;
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}
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for (i = 0; i < num_channels; i++) {
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if (chans[i] >= adc->cfg->max_channels) {
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dev_err(dev, "bad channel %u\n", chans[i]);
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return -EINVAL;
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}
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uc_pdata->channel_mask |= 1 << chans[i];
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}
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return ret;
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}
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static int stm32_adc_generic_chan_init(struct udevice *dev, unsigned int num_channels)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct stm32_adc *adc = dev_get_priv(dev);
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ofnode child;
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int val, ret;
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ofnode_for_each_subnode(child, dev_ofnode(dev)) {
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ret = ofnode_read_u32(child, "reg", &val);
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if (ret) {
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dev_err(dev, "Missing channel index %d\n", ret);
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return ret;
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}
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if (val >= adc->cfg->max_channels) {
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dev_err(dev, "Invalid channel %d\n", val);
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return -EINVAL;
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}
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uc_pdata->channel_mask |= 1 << val;
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}
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return 0;
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}
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static int stm32_adc_chan_of_init(struct udevice *dev)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct stm32_adc *adc = dev_get_priv(dev);
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unsigned int num_channels;
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int ret;
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bool legacy = false;
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num_channels = dev_get_child_count(dev);
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/* If no channels have been found, fallback to channels legacy properties. */
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if (!num_channels) {
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legacy = true;
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ret = stm32_adc_get_legacy_chan_count(dev);
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if (!ret) {
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dev_err(dev, "No channel found\n");
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return -ENODATA;
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} else if (ret < 0) {
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return ret;
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}
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num_channels = ret;
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}
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if (num_channels > adc->cfg->max_channels) {
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dev_err(dev, "too many st,adc-channels: %d\n", num_channels);
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return -EINVAL;
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}
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if (legacy)
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ret = stm32_adc_legacy_chan_init(dev, num_channels);
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else
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ret = stm32_adc_generic_chan_init(dev, num_channels);
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if (ret < 0)
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return ret;
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uc_pdata->data_mask = (1 << adc->cfg->num_bits) - 1;
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uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
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uc_pdata->data_timeout_us = 100000;
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return 0;
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}
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static int stm32_adc_probe(struct udevice *dev)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
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struct stm32_adc *adc = dev_get_priv(dev);
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int offset, ret;
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offset = dev_read_u32_default(dev, "reg", -ENODATA);
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if (offset < 0) {
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dev_err(dev, "Can't read reg property\n");
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return offset;
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}
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adc->regs = common->base + offset;
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adc->cfg = (const struct stm32_adc_cfg *)dev_get_driver_data(dev);
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/* VDD supplied by common vref pin */
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uc_pdata->vdd_supply = common->vref;
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uc_pdata->vdd_microvolts = common->vref_uv;
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uc_pdata->vss_microvolts = 0;
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ret = stm32_adc_chan_of_init(dev);
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if (ret < 0)
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return ret;
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ret = stm32_adc_exit_pwr_down(dev);
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if (ret < 0)
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return ret;
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ret = stm32_adc_selfcalib(dev);
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if (ret)
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stm32_adc_enter_pwr_down(dev);
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return ret;
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}
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static const struct adc_ops stm32_adc_ops = {
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.start_channel = stm32_adc_start_channel,
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.channel_data = stm32_adc_channel_data,
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.stop = stm32_adc_stop,
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};
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static const struct stm32_adc_cfg stm32h7_adc_cfg = {
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.num_bits = 16,
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.max_channels = STM32_ADC_CH_MAX,
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};
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static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
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.num_bits = 16,
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.max_channels = STM32_ADC_CH_MAX,
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.has_vregready = true,
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};
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static const struct udevice_id stm32_adc_ids[] = {
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{ .compatible = "st,stm32h7-adc",
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.data = (ulong)&stm32h7_adc_cfg },
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{ .compatible = "st,stm32mp1-adc",
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.data = (ulong)&stm32mp1_adc_cfg },
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{}
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};
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U_BOOT_DRIVER(stm32_adc) = {
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.name = "stm32-adc",
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.id = UCLASS_ADC,
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.of_match = stm32_adc_ids,
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.probe = stm32_adc_probe,
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.ops = &stm32_adc_ops,
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.priv_auto = sizeof(struct stm32_adc),
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};
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