mirror of
https://github.com/AsahiLinux/u-boot
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22e6440586
Rather than bang MMRs directly, use the new portmux framework to handle the details. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
434 lines
10 KiB
C
434 lines
10 KiB
C
/*
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* video.c - run splash screen on lcd
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*
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* Copyright (c) 2007-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <stdarg.h>
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#include <common.h>
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#include <config.h>
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#include <malloc.h>
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#include <asm/blackfin.h>
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#include <asm/portmux.h>
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#include <asm/mach-common/bits/dma.h>
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#include <spi.h>
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#include <linux/types.h>
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#include <stdio_dev.h>
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#include <asm/mach-common/bits/ppi.h>
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#include <asm/mach-common/bits/timer.h>
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#define LCD_X_RES 320 /* Horizontal Resolution */
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#define LCD_Y_RES 240 /* Vertical Resolution */
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#define DMA_BUS_SIZE 16
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#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 /* lq035q1 */
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#if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \
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!defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI)
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# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
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#endif
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/* Interface 16/18-bit TFT over an 8-bit wide PPI using a
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* small Programmable Logic Device (CPLD)
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* http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
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*/
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#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
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#include <asm/bfin_logo_rgb565_230x230.h>
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#define LCD_BPP 16 /* Bit Per Pixel */
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#define CLOCKS_PPIX 2 /* Clocks per pixel */
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#define CPLD_DELAY 3 /* RGB565 pipeline delay */
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#endif
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#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
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#include <asm/bfin_logo_230x230.h>
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#define LCD_BPP 24 /* Bit Per Pixel */
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#define CLOCKS_PPIX 3 /* Clocks per pixel */
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#define CPLD_DELAY 5 /* RGB888 pipeline delay */
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#endif
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/*
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* HS and VS timing parameters (all in number of PPI clk ticks)
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*/
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#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
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#define H_PERIOD (336 * CLOCKS_PPIX) /* HS period */
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#define H_PULSE (2 * CLOCKS_PPIX) /* HS pulse width */
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#define H_START (7 * CLOCKS_PPIX + CPLD_DELAY) /* first valid pixel */
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#define U_LINE 4 /* Blanking Lines */
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#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
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#define V_PULSE (2 * CLOCKS_PPIX) /* VS pulse width (1-5 H_PERIODs) */
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#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
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#define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
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/*
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* LCD Modes
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*/
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#define LQ035_RL (0 << 8) /* Right -> Left Scan */
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#define LQ035_LR (1 << 8) /* Left -> Right Scan */
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#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
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#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
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#define LQ035_BGR (1 << 11) /* Use BGR format */
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#define LQ035_RGB (0 << 11) /* Use RGB format */
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#define LQ035_NORM (1 << 13) /* Reversal */
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#define LQ035_REV (0 << 13) /* Reversal */
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#define LQ035_INDEX 0x74
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#define LQ035_DATA 0x76
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#define LQ035_DRIVER_OUTPUT_CTL 0x1
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#define LQ035_SHUT_CTL 0x11
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#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
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#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
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#define LQ035_SHUT (1 << 0) /* Shutdown */
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#define LQ035_ON (0 << 0) /* Shutdown */
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#ifndef CONFIG_LQ035Q1_LCD_MODE
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#define CONFIG_LQ035Q1_LCD_MODE (LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
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#endif
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#else /* t350mcqb */
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#include <asm/bfin_logo_230x230.h>
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#define LCD_BPP 24 /* Bit Per Pixel */
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#define CLOCKS_PPIX 3 /* Clocks per pixel */
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/* HS and VS timing parameters (all in number of PPI clk ticks) */
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#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
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#define H_PERIOD (408 * CLOCKS_PPIX) /* HS period */
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#define H_PULSE 90 /* HS pulse width */
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#define H_START 204 /* first valid pixel */
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#define U_LINE 1 /* Blanking Lines */
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#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
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#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
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#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
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#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
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#endif
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#define LCD_PIXEL_SIZE (LCD_BPP / 8)
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#define DMA_SIZE16 2
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#define PPI_TX_MODE 0x2
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#define PPI_XFER_TYPE_11 0xC
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#define PPI_PORT_CFG_01 0x10
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#define PPI_PACK_EN 0x80
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#define PPI_POLS_1 0x8000
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#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
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static struct spi_slave *slave;
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static int lq035q1_control(unsigned char reg, unsigned short value)
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{
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int ret;
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u8 regs[3] = {LQ035_INDEX, 0, 0};
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u8 data[3] = {LQ035_DATA, 0, 0};
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u8 dummy[3];
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regs[2] = reg;
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data[1] = value >> 8;
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data[2] = value & 0xFF;
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if (!slave) {
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/* FIXME: Verify the max SCK rate */
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slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
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CONFIG_LQ035Q1_SPI_CS, 20000000,
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SPI_MODE_3);
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if (!slave)
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return -1;
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}
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if (spi_claim_bus(slave))
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return -1;
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ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
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ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
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spi_release_bus(slave);
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return ret;
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}
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#endif
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/* enable and disable PPI functions */
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void EnablePPI(void)
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{
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*pPPI_CONTROL |= PORT_EN;
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}
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void DisablePPI(void)
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{
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*pPPI_CONTROL &= ~PORT_EN;
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}
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void Init_Ports(void)
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{
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const unsigned short pins[] = {
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P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
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P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
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};
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peripheral_request_list(pins, "lcd");
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}
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void Init_PPI(void)
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{
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*pPPI_DELAY = H_START;
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*pPPI_COUNT = (H_ACTPIX-1);
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*pPPI_FRAME = V_LINES;
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/* PPI control, to be replaced with definitions */
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*pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */
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PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
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PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
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PPI_PACK_EN | /* packing enabled PACK_EN */
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PPI_POLS_1; /* faling edge syncs POLS */
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}
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void Init_DMA(void *dst)
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{
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*pDMA0_START_ADDR = dst;
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/* X count */
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*pDMA0_X_COUNT = H_ACTPIX / 2;
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*pDMA0_X_MODIFY = DMA_BUS_SIZE / 8;
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/* Y count */
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*pDMA0_Y_COUNT = V_LINES;
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*pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8;
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/* DMA Config */
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*pDMA0_CONFIG =
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WDSIZE_16 | /* 16 bit DMA */
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DMA2D | /* 2D DMA */
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FLOW_AUTO; /* autobuffer mode */
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}
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void EnableDMA(void)
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{
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*pDMA0_CONFIG |= DMAEN;
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}
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void DisableDMA(void)
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{
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*pDMA0_CONFIG &= ~DMAEN;
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}
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/* Init TIMER0 as Frame Sync 1 generator */
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void InitTIMER0(void)
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{
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*pTIMER_DISABLE |= TIMDIS0; /* disable Timer */
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SSYNC();
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*pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */
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SSYNC();
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*pTIMER0_PERIOD = H_PERIOD;
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SSYNC();
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*pTIMER0_WIDTH = H_PULSE;
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SSYNC();
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*pTIMER0_CONFIG = PWM_OUT |
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PERIOD_CNT |
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TIN_SEL |
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CLK_SEL |
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EMU_RUN;
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SSYNC();
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}
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void EnableTIMER0(void)
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{
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*pTIMER_ENABLE |= TIMEN0;
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SSYNC();
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}
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void DisableTIMER0(void)
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{
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*pTIMER_DISABLE |= TIMDIS0;
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SSYNC();
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}
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void InitTIMER1(void)
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{
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*pTIMER_DISABLE |= TIMDIS1; /* disable Timer */
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SSYNC();
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*pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */
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SSYNC();
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*pTIMER1_PERIOD = V_PERIOD;
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SSYNC();
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*pTIMER1_WIDTH = V_PULSE;
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SSYNC();
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*pTIMER1_CONFIG = PWM_OUT |
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PERIOD_CNT |
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TIN_SEL |
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CLK_SEL |
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EMU_RUN;
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SSYNC();
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}
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void EnableTIMER1(void)
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{
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*pTIMER_ENABLE |= TIMEN1;
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SSYNC();
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}
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void DisableTIMER1(void)
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{
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*pTIMER_DISABLE |= TIMDIS1;
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SSYNC();
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}
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void EnableTIMER12(void)
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{
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*pTIMER_ENABLE |= TIMEN1 | TIMEN0;
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SSYNC();
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}
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int video_init(void *dst)
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{
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#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
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lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
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lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
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LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
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#endif
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Init_Ports();
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Init_DMA(dst);
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EnableDMA();
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InitTIMER0();
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InitTIMER1();
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Init_PPI();
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EnablePPI();
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#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
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EnableTIMER12();
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#else
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/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
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EnableTIMER1();
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/* Add Some Delay ... */
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SSYNC();
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SSYNC();
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SSYNC();
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SSYNC();
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/* now start frame sync 1 */
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EnableTIMER0();
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#endif
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return 0;
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}
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static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
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{
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if (dcache_status())
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blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
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bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
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/* Setup destination start address */
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bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
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+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
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/* Setup destination xcount */
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bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
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/* Setup destination xmodify */
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bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
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/* Setup destination ycount */
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bfin_write_MDMA_D0_Y_COUNT(logo->height);
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/* Setup destination ymodify */
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bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
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/* Setup Source start address */
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bfin_write_MDMA_S0_START_ADDR(logo->data);
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/* Setup Source xcount */
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bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
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/* Setup Source xmodify */
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bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
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/* Setup Source ycount */
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bfin_write_MDMA_S0_Y_COUNT(logo->height);
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/* Setup Source ymodify */
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bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
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/* Enable source DMA */
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bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
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SSYNC();
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bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
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while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
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bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
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bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
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}
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void video_putc(const char c)
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{
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}
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void video_puts(const char *s)
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{
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}
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int drv_video_init(void)
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{
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int error, devices = 1;
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struct stdio_dev videodev;
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u8 *dst;
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u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
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dst = malloc(fbmem_size);
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if (dst == NULL) {
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printf("Failed to alloc FB memory\n");
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return -1;
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}
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#ifdef EASYLOGO_ENABLE_GZIP
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unsigned char *data = EASYLOGO_DECOMP_BUFFER;
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unsigned long src_len = EASYLOGO_ENABLE_GZIP;
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if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
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puts("Failed to decompress logo\n");
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free(dst);
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return -1;
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}
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bfin_logo.data = data;
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#endif
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memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
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dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
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(LCD_X_RES - bfin_logo.width) / 2,
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(LCD_Y_RES - bfin_logo.height) / 2);
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video_init(dst); /* Video initialization */
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memset(&videodev, 0, sizeof(videodev));
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strcpy(videodev.name, "video");
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videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
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videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
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videodev.putc = video_putc; /* 'putc' function */
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videodev.puts = video_puts; /* 'puts' function */
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error = stdio_register(&videodev);
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return (error == 0) ? devices : error;
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}
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