mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 14:53:06 +00:00
3d91bc90de
On branch WIP/17Oct2023, the EEPROM can no longer be read:
U-Boot 2023.10-latest (Oct 17 2023 - 15:53:43 -0400)
CPU: Freescale i.MX8MNano Quad rev1.0 at 1200 MHz
Reset cause: POR
Model: Variscite VAR-SOM-MX8MN Symphony evaluation board
var_read_som_eeprom: uclass_get_device_by_of_offset() failed: -19
initcall failed at call 000000004022207c (err=-19)
Convert EEPROM-related properties to bootph-all so that the EEPROM can
also be read outside of SPL.
Fixes: 9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
87 lines
969 B
Text
87 lines
969 B
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 Collabora Ltd.
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*/
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#include "imx8mn-u-boot.dtsi"
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
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bootph-pre-ram;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
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bootph-pre-ram;
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};
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&eeprom_som {
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#address-cells = <1>;
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#size-cells = <1>;
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eth_mac_address: eth-mac-address@19 {
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reg = <0x19 0x06>;
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};
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};
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&fec1 {
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nvmem-cells = <ð_mac_address>;
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nvmem-cell-names = "mac-address";
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&i2c1 {
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bootph-all;
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};
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&pinctrl_i2c1 {
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bootph-all;
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};
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&pinctrl_pmic {
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bootph-pre-ram;
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};
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&pinctrl_reg_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart4 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_wdog {
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bootph-pre-ram;
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};
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&uart4 {
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bootph-pre-ram;
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};
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&usdhc2 {
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bootph-pre-ram;
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};
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&usdhc3 {
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bootph-pre-ram;
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};
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&eeprom_som {
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bootph-all;
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};
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