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https://github.com/AsahiLinux/u-boot
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e0056b3410
Based on the original S3C64XX NAND driver by Samsung for U-Boot 1.1.6. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
319 lines
7.9 KiB
C
319 lines
7.9 KiB
C
/*
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* (C) Copyright 2006 DENX Software Engineering
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*
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* Implementation for U-Boot 1.1.6 by Samsung
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*
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* (C) Copyright 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#include <s3c6400.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#define MAX_CHIPS 2
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static int nand_cs[MAX_CHIPS] = {0, 1};
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#ifdef CONFIG_NAND_SPL
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#define printf(arg...) do {} while (0)
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#endif
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/* Nand flash definition values by jsgood */
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#ifdef S3C_NAND_DEBUG
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/*
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* Function to print out oob buffer for debugging
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* Written by jsgood
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*/
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static void print_oob(const char *header, struct mtd_info *mtd)
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{
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int i;
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struct nand_chip *chip = mtd->priv;
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printf("%s:\t", header);
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for (i = 0; i < 64; i++)
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printf("%02x ", chip->oob_poi[i]);
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printf("\n");
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}
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#endif /* S3C_NAND_DEBUG */
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#ifdef CONFIG_NAND_SPL
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static u_char nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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return readb(this->IO_ADDR_R);
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}
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static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i = 0; i < len; i++)
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writeb(buf[i], this->IO_ADDR_W);
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}
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static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i = 0; i < len; i++)
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buf[i] = readb(this->IO_ADDR_R);
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}
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#endif
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static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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int ctrl = readl(NFCONT);
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switch (chip) {
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case -1:
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ctrl |= 6;
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break;
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case 0:
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ctrl &= ~2;
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break;
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case 1:
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ctrl &= ~4;
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break;
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default:
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return;
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}
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writel(ctrl, NFCONT);
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}
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/*
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* Hardware specific access to control-lines function
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* Written by jsgood
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*/
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static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_CLE)
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this->IO_ADDR_W = (void __iomem *)NFCMMD;
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else if (ctrl & NAND_ALE)
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this->IO_ADDR_W = (void __iomem *)NFADDR;
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else
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this->IO_ADDR_W = (void __iomem *)NFDATA;
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if (ctrl & NAND_NCE)
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s3c_nand_select_chip(mtd, *(int *)this->priv);
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else
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s3c_nand_select_chip(mtd, -1);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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/*
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* Function for checking device ready pin
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* Written by jsgood
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*/
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static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
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{
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return !!(readl(NFSTAT) & NFSTAT_RnB);
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}
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#ifdef CFG_S3C_NAND_HWECC
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/*
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* This function is called before encoding ecc codes to ready ecc engine.
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* Written by jsgood
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*/
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static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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u_long nfcont, nfconf;
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/*
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* The original driver used 4-bit ECC for "new" MLC chips, i.e., for
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* those with non-zero ID[3][3:2], which anyway only holds for ST
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* (Numonyx) chips
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*/
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nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT;
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writel(nfconf, NFCONF);
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/* Initialize & unlock */
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nfcont = readl(NFCONT);
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nfcont |= NFCONT_INITECC;
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nfcont &= ~NFCONT_MECCLOCK;
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if (mode == NAND_ECC_WRITE)
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nfcont |= NFCONT_ECC_ENC;
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else if (mode == NAND_ECC_READ)
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nfcont &= ~NFCONT_ECC_ENC;
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writel(nfcont, NFCONT);
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}
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/*
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* This function is called immediately after encoding ecc codes.
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* This function returns encoded ecc codes.
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* Written by jsgood
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*/
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static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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u_char *ecc_code)
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{
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u_long nfcont, nfmecc0;
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/* Lock */
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nfcont = readl(NFCONT);
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nfcont |= NFCONT_MECCLOCK;
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writel(nfcont, NFCONT);
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nfmecc0 = readl(NFMECC0);
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ecc_code[0] = nfmecc0 & 0xff;
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ecc_code[1] = (nfmecc0 >> 8) & 0xff;
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ecc_code[2] = (nfmecc0 >> 16) & 0xff;
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ecc_code[3] = (nfmecc0 >> 24) & 0xff;
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return 0;
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}
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/*
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* This function determines whether read data is good or not.
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* If SLC, must write ecc codes to controller before reading status bit.
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* If MLC, status bit is already set, so only reading is needed.
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* If status bit is good, return 0.
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* If correctable errors occured, do that.
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* If uncorrectable errors occured, return -1.
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* Written by jsgood
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*/
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static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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int ret = -1;
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u_long nfestat0, nfmeccdata0, nfmeccdata1, err_byte_addr;
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u_char err_type, repaired;
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/* SLC: Write ecc to compare */
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nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0];
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nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2];
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writel(nfmeccdata0, NFMECCDATA0);
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writel(nfmeccdata1, NFMECCDATA1);
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/* Read ecc status */
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nfestat0 = readl(NFESTAT0);
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err_type = nfestat0 & 0x3;
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switch (err_type) {
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case 0: /* No error */
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ret = 0;
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break;
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case 1:
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/*
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* 1 bit error (Correctable)
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* (nfestat0 >> 7) & 0x7ff :error byte number
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* (nfestat0 >> 4) & 0x7 :error bit number
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*/
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err_byte_addr = (nfestat0 >> 7) & 0x7ff;
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repaired = dat[err_byte_addr] ^ (1 << ((nfestat0 >> 4) & 0x7));
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printf("S3C NAND: 1 bit error detected at byte %ld. "
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"Correcting from 0x%02x to 0x%02x...OK\n",
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err_byte_addr, dat[err_byte_addr], repaired);
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dat[err_byte_addr] = repaired;
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ret = 1;
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break;
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case 2: /* Multiple error */
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case 3: /* ECC area error */
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printf("S3C NAND: ECC uncorrectable error detected. "
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"Not correctable.\n");
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ret = -1;
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break;
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}
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return ret;
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}
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#endif /* CFG_S3C_NAND_HWECC */
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/*
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* Board-specific NAND initialization. The following members of the
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* argument are board-specific (per include/linux/mtd/nand.h):
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* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
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* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
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* - hwcontrol: hardwarespecific function for accesing control-lines
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* - dev_ready: hardwarespecific function for accesing device ready/busy line
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* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
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* only be provided if a hardware ECC is available
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* - eccmode: mode of ecc, see defines
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* - chip_delay: chip dependent delay for transfering data from array to
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* read regs (tR)
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* - options: various chip options. They can partly be set to inform
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* nand_scan about special functionality. See the defines for further
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* explanation
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* Members with a "?" were not set in the merged testing-NAND branch,
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* so they are not set here either.
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*/
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int board_nand_init(struct nand_chip *nand)
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{
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static int chip_n;
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if (chip_n >= MAX_CHIPS)
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return -ENODEV;
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NFCONT_REG = (NFCONT_REG & ~NFCONT_WP) | NFCONT_ENABLE | 0x6;
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nand->IO_ADDR_R = (void __iomem *)NFDATA;
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nand->IO_ADDR_W = (void __iomem *)NFDATA;
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nand->cmd_ctrl = s3c_nand_hwcontrol;
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nand->dev_ready = s3c_nand_device_ready;
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nand->select_chip = s3c_nand_select_chip;
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nand->options = 0;
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#ifdef CONFIG_NAND_SPL
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nand->read_byte = nand_read_byte;
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nand->write_buf = nand_write_buf;
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nand->read_buf = nand_read_buf;
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#endif
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#ifdef CFG_S3C_NAND_HWECC
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nand->ecc.hwctl = s3c_nand_enable_hwecc;
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nand->ecc.calculate = s3c_nand_calculate_ecc;
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nand->ecc.correct = s3c_nand_correct_data;
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/*
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* If you get more than 1 NAND-chip with different page-sizes on the
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* board one day, it will get more complicated...
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*/
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.size = CFG_NAND_ECCSIZE;
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nand->ecc.bytes = CFG_NAND_ECCBYTES;
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#else
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nand->ecc.mode = NAND_ECC_SOFT;
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#endif /* ! CFG_S3C_NAND_HWECC */
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nand->priv = nand_cs + chip_n++;
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return 0;
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}
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