u-boot/arch/arm/include/asm/arch-rockchip/cru.h
Jagan Teki e230c579a3 rockchip: Separate the reset cause from display cpuinfo
reset cause is a generic functionality based on the soc
cru registers in rockchip. This can be used for printing
the cause of reset in cpuinfo or some other place where
reset cause is needed. 

Other than cpuinfo, reset cause can also be using during
bootcount for checking the specific reset cause and glow
the led based on the reset cause.

So, let's separate the reset cause code from cpuinfo, and
add a check to build it for rk3399, rk3288 since these two
soc are supporting reset cause as of now.

Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00

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C

/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* (C) Copyright 2019 Amarula Solutions.
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
#ifndef _ROCKCHIP_CLOCK_H
#define _ROCKCHIP_CLOCK_H
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
#endif
#if defined(CONFIG_ROCKCHIP_RK3288)
# include <asm/arch-rockchip/cru_rk3288.h>
#elif defined(CONFIG_ROCKCHIP_RK3399)
# include <asm/arch-rockchip/cru_rk3399.h>
#endif
/* CRU_GLB_RST_ST */
enum {
GLB_POR_RST,
FST_GLB_RST_ST = BIT(0),
SND_GLB_RST_ST = BIT(1),
FST_GLB_TSADC_RST_ST = BIT(2),
SND_GLB_TSADC_RST_ST = BIT(3),
FST_GLB_WDT_RST_ST = BIT(4),
SND_GLB_WDT_RST_ST = BIT(5),
};
#define MHz 1000000
char *get_reset_cause(void);
#endif /* _ROCKCHIP_CLOCK_H */