mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 09:30:10 +00:00
76abfa5781
When the u-boot address of destination equal to __start, no relocation. relocation offset(r9) = 0. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Tested-by: Stefano Babic <sbabic@denx.de>
608 lines
14 KiB
ArmAsm
608 lines
14 KiB
ArmAsm
/*
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* armboot - Startup Code for XScale CPU-core
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*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
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* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
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* Copyright (C) 2001 Marius Groger <mag@sysgo.de>
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* Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
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* Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
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* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
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* Copyright (C) 2003 Kshitij <kshitij@ti.com>
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* Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
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* Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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#ifdef CONFIG_CPU_PXA25X
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#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
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#error "Init SP address must be set to 0xfffff800 for PXA250"
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#endif
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#endif
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.globl _start
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_start: b reset
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#ifdef CONFIG_SPL_BUILD
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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_hang:
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.word do_hang
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678 /* now 16*4=64 */
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#else
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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_pad: .word 0x12345678 /* now 16*4=64 */
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#endif /* CONFIG_SPL_BUILD */
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.global _end_vect
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_end_vect:
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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.globl _TEXT_BASE
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_TEXT_BASE:
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#ifdef CONFIG_SPL_BUILD
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.word CONFIG_SPL_TEXT_BASE
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#else
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.word CONFIG_SYS_TEXT_BASE
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#endif
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/*
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* These are defined in the board-specific linker script.
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* Subtracting _start from them lets the linker put their
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* relative position in the executable instead of leaving
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* them null.
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*/
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.globl _bss_start_ofs
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_bss_start_ofs:
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.word __bss_start - _start
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.globl _bss_end_ofs
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_bss_end_ofs:
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.word __bss_end__ - _start
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.globl _end_ofs
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_end_ofs:
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.word _end - _start
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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#ifdef CONFIG_CPU_PXA25X
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bl lock_cache_for_stack
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#endif
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/* Set stackpointer in internal RAM to call board_init_f */
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call_board_init_f:
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ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
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bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
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ldr r0, =0x00000000
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bl board_init_f
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/*------------------------------------------------------------------------------*/
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#ifndef CONFIG_SPL_BUILD
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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*/
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.globl relocate_code
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relocate_code:
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mov r4, r0 /* save addr_sp */
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mov r5, r1 /* save addr of gd */
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mov r6, r2 /* save addr of destination */
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/* Set up the stack */
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stack_setup:
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mov sp, r4
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/* Disable the Dcache RAM lock for stack now */
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#ifdef CONFIG_CPU_PXA25X
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bl cpu_init_crit
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#endif
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adr r0, _start
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cmp r0, r6
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moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
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beq clear_bss /* skip relocation */
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mov r1, r6 /* r1 <- scratch for copy_loop */
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ldr r3, _bss_start_ofs
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add r2, r0, r3 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r9-r10} /* copy from source address [r0] */
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stmia r1!, {r9-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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blo copy_loop
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#ifndef CONFIG_SPL_BUILD
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/*
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* fix .rel.dyn relocations
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*/
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ldr r0, _TEXT_BASE /* r0 <- Text base */
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sub r9, r6, r0 /* r9 <- relocation offset */
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ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
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add r10, r10, r0 /* r10 <- sym table in FLASH */
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ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
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add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
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ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
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add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
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fixloop:
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ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
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add r0, r0, r9 /* r0 <- location to fix up in RAM */
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ldr r1, [r2, #4]
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and r7, r1, #0xff
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cmp r7, #23 /* relative fixup? */
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beq fixrel
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cmp r7, #2 /* absolute fixup? */
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beq fixabs
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/* ignore unknown type of fixup */
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b fixnext
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fixabs:
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/* absolute fix: set location to (offset) symbol value */
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mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
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add r1, r10, r1 /* r1 <- address of symbol in table */
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ldr r1, [r1, #4] /* r1 <- symbol value */
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add r1, r1, r9 /* r1 <- relocated sym addr */
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b fixnext
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fixrel:
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/* relative fix: increase location by offset */
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ldr r1, [r0]
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add r1, r1, r9
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fixnext:
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str r1, [r0]
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add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
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cmp r2, r3
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blo fixloop
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#endif
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clear_bss:
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#ifndef CONFIG_SPL_BUILD
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ldr r0, _bss_start_ofs
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ldr r1, _bss_end_ofs
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mov r4, r6 /* reloc addr */
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add r0, r0, r4
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add r1, r1, r4
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mov r2, #0x00000000 /* clear */
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clbss_l:cmp r0, r1 /* clear loop... */
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bhs clbss_e /* if reached end of bss, exit */
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str r2, [r0]
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add r0, r0, #4
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b clbss_l
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clbss_e:
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#endif /* #ifndef CONFIG_SPL_BUILD */
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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#ifdef CONFIG_ONENAND_SPL
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ldr r0, _onenand_boot_ofs
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mov pc, r0
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_onenand_boot_ofs:
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.word onenand_boot
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#else
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jump_2_ram:
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ldr r0, _board_init_r_ofs
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ldr r1, _TEXT_BASE
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add lr, r0, r1
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add lr, lr, r9
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/* setup parameters for board_init_r */
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mov r0, r5 /* gd_t */
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mov r1, r6 /* dest_addr */
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/* jump to it ... */
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mov pc, lr
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_board_init_r_ofs:
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.word board_init_r - _start
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#endif
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_rel_dyn_start_ofs:
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.word __rel_dyn_start - _start
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_rel_dyn_end_ofs:
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.word __rel_dyn_end - _start
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_dynsym_start_ofs:
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.word __dynsym_start - _start
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#endif
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr /* back to my caller */
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#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
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#ifndef CONFIG_SPL_BUILD
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
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*/
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
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stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
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ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
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ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
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add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
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mov r0, sp @ save current stack into r0 (param register)
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm
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.macro get_bad_stack
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ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
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str lr, [r13] @ save caller lr in position 0 of saved stack
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mrs lr, spsr @ get the spsr
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str lr, [r13, #4] @ save spsr in position 1 of saved stack
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mov r13, #MODE_SVC @ prepare SVC-Mode
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@ msr spsr_c, r13
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msr spsr, r13 @ switch modes, make sure moves will execute
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mov lr, pc @ capture return pc
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movs pc, lr @ jump to next instruction & switch modes.
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.endm
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.macro get_bad_stack_swi
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sub r13, r13, #4 @ space on current stack for scratch reg.
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str r0, [r13] @ save R0's value.
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ldr r0, IRQ_STACK_START_IN @ get data regions start
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str lr, [r0] @ save caller lr in position 0 of saved stack
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mrs r0, spsr @ get the spsr
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str lr, [r0, #4] @ save spsr in position 1 of saved stack
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ldr r0, [r13] @ restore r0
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add r13, r13, #4 @ pop stack entry
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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#endif /* CONFIG_SPL_BUILD */
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/*
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* exception handlers
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*/
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#ifdef CONFIG_SPL_BUILD
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.align 5
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do_hang:
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ldr sp, _TEXT_BASE /* use 32 words about stack */
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bl hang /* hang and never return */
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#else /* !CONFIG_SPL_BUILD */
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack_swi
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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#ifdef CONFIG_USE_IRQ
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.align 5
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irq:
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get_irq_stack
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irq_save_user_regs
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bl do_irq
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irq_restore_user_regs
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.align 5
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fiq:
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get_fiq_stack
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/* someone ought to write a more effiction fiq_save_user_regs */
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irq_save_user_regs
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bl do_fiq
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irq_restore_user_regs
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#else
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
|
|
bl do_irq
|
|
|
|
.align 5
|
|
fiq:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_fiq
|
|
|
|
#endif
|
|
.align 5
|
|
#endif /* CONFIG_SPL_BUILD */
|
|
|
|
|
|
/*
|
|
* Enable MMU to use DCache as DRAM.
|
|
*
|
|
* This is useful on PXA25x and PXA26x in early bootstages, where there is no
|
|
* other possible memory available to hold stack.
|
|
*/
|
|
#ifdef CONFIG_CPU_PXA25X
|
|
.macro CPWAIT reg
|
|
mrc p15, 0, \reg, c2, c0, 0
|
|
mov \reg, \reg
|
|
sub pc, pc, #4
|
|
.endm
|
|
lock_cache_for_stack:
|
|
/* Domain access -- enable for all CPs */
|
|
ldr r0, =0x0000ffff
|
|
mcr p15, 0, r0, c3, c0, 0
|
|
|
|
/* Point TTBR to MMU table */
|
|
ldr r0, =mmutable
|
|
mcr p15, 0, r0, c2, c0, 0
|
|
|
|
/* Kick in MMU, ICache, DCache, BTB */
|
|
mrc p15, 0, r0, c1, c0, 0
|
|
bic r0, #0x1b00
|
|
bic r0, #0x0087
|
|
orr r0, #0x1800
|
|
orr r0, #0x0005
|
|
mcr p15, 0, r0, c1, c0, 0
|
|
CPWAIT r0
|
|
|
|
/* Unlock Icache, Dcache */
|
|
mcr p15, 0, r0, c9, c1, 1
|
|
mcr p15, 0, r0, c9, c2, 1
|
|
|
|
/* Flush Icache, Dcache, BTB */
|
|
mcr p15, 0, r0, c7, c7, 0
|
|
|
|
/* Unlock I-TLB, D-TLB */
|
|
mcr p15, 0, r0, c10, c4, 1
|
|
mcr p15, 0, r0, c10, c8, 1
|
|
|
|
/* Flush TLB */
|
|
mcr p15, 0, r0, c8, c7, 0
|
|
|
|
/* Allocate 4096 bytes of Dcache as RAM */
|
|
|
|
/* Drain pending loads and stores */
|
|
mcr p15, 0, r0, c7, c10, 4
|
|
|
|
mov r4, #0x00
|
|
mov r5, #0x00
|
|
mov r2, #0x01
|
|
mcr p15, 0, r0, c9, c2, 0
|
|
CPWAIT r0
|
|
|
|
/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
|
|
mov r0, #128
|
|
ldr r1, =0xfffff000
|
|
|
|
alloc:
|
|
mcr p15, 0, r1, c7, c2, 5
|
|
/* Drain pending loads and stores */
|
|
mcr p15, 0, r0, c7, c10, 4
|
|
strd r4, [r1], #8
|
|
strd r4, [r1], #8
|
|
strd r4, [r1], #8
|
|
strd r4, [r1], #8
|
|
subs r0, #0x01
|
|
bne alloc
|
|
/* Drain pending loads and stores */
|
|
mcr p15, 0, r0, c7, c10, 4
|
|
mov r2, #0x00
|
|
mcr p15, 0, r2, c9, c2, 0
|
|
CPWAIT r0
|
|
|
|
mov pc, lr
|
|
|
|
.section .mmutable, "a"
|
|
mmutable:
|
|
.align 14
|
|
/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
|
|
.set __base, 0
|
|
.rept 0xfff
|
|
.word (__base << 20) | 0xc12
|
|
.set __base, __base + 1
|
|
.endr
|
|
|
|
/* 0xfff00000 : 1:1, cached mapping */
|
|
.word (0xfff << 20) | 0x1c1e
|
|
#endif /* CONFIG_CPU_PXA25X */
|