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https://github.com/AsahiLinux/u-boot
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702395073f
Certain modules are not affected by means of a warm reset and need not be configured again. Adding an API to detect the reset reason warm/cold. This will be used to skip the module configurations that are retained across a warm reset. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
241 lines
7.8 KiB
C
241 lines
7.8 KiB
C
/*
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* cpu.h
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*
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* AM33xx specific header file
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _AM33XX_CPU_H
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#define _AM33XX_CPU_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#include <asm/arch/hardware.h>
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#define BIT(x) (1 << x)
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#define CL_BIT(x) (0 << x)
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/* Timer register bits */
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#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
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#define TCLR_AR BIT(1) /* Auto reload */
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#define TCLR_PRE BIT(5) /* Pre-scaler enable */
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#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
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#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
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/* device type */
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#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
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#define TST_DEVICE 0x0
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#define EMU_DEVICE 0x1
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#define HS_DEVICE 0x2
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#define GP_DEVICE 0x3
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/* cpu-id for AM33XX family */
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#define AM335X 0xB944
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#define DEVICE_ID 0x44E10600
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/* This gives the status of the boot mode pins on the evm */
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#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
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| BIT(3) | BIT(4))
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/* Reset control */
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#ifdef CONFIG_AM33XX
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#define PRM_RSTCTRL 0x44E00F00
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#define PRM_RSTST 0x44E00F08
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#endif
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#define PRM_RSTCTRL_RESET 0x01
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#define PRM_RSTST_WARM_RESET_MASK 0x232
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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/* Encapsulating core pll registers */
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struct cm_wkuppll {
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unsigned int wkclkstctrl; /* offset 0x00 */
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unsigned int wkctrlclkctrl; /* offset 0x04 */
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unsigned int wkgpio0clkctrl; /* offset 0x08 */
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unsigned int wkl4wkclkctrl; /* offset 0x0c */
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unsigned int resv2[4];
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unsigned int idlestdpllmpu; /* offset 0x20 */
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unsigned int resv3[2];
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unsigned int clkseldpllmpu; /* offset 0x2c */
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unsigned int resv4[1];
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unsigned int idlestdpllddr; /* offset 0x34 */
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unsigned int resv5[2];
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unsigned int clkseldpllddr; /* offset 0x40 */
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unsigned int resv6[4];
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unsigned int clkseldplldisp; /* offset 0x54 */
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unsigned int resv7[1];
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unsigned int idlestdpllcore; /* offset 0x5c */
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unsigned int resv8[2];
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unsigned int clkseldpllcore; /* offset 0x68 */
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unsigned int resv9[1];
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unsigned int idlestdpllper; /* offset 0x70 */
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unsigned int resv10[3];
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unsigned int divm4dpllcore; /* offset 0x80 */
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unsigned int divm5dpllcore; /* offset 0x84 */
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unsigned int clkmoddpllmpu; /* offset 0x88 */
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unsigned int clkmoddpllper; /* offset 0x8c */
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unsigned int clkmoddpllcore; /* offset 0x90 */
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unsigned int clkmoddpllddr; /* offset 0x94 */
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unsigned int clkmoddplldisp; /* offset 0x98 */
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unsigned int clkseldpllper; /* offset 0x9c */
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unsigned int divm2dpllddr; /* offset 0xA0 */
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unsigned int divm2dplldisp; /* offset 0xA4 */
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unsigned int divm2dpllmpu; /* offset 0xA8 */
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unsigned int divm2dpllper; /* offset 0xAC */
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unsigned int resv11[1];
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unsigned int wkup_uart0ctrl; /* offset 0xB4 */
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unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
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unsigned int resv12[7];
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unsigned int divm6dpllcore; /* offset 0xD8 */
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};
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/**
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* Encapsulating peripheral functional clocks
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* pll registers
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*/
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struct cm_perpll {
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unsigned int l4lsclkstctrl; /* offset 0x00 */
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unsigned int l3sclkstctrl; /* offset 0x04 */
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unsigned int l4fwclkstctrl; /* offset 0x08 */
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unsigned int l3clkstctrl; /* offset 0x0c */
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unsigned int resv1;
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unsigned int cpgmac0clkctrl; /* offset 0x14 */
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unsigned int lcdclkctrl; /* offset 0x18 */
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unsigned int usb0clkctrl; /* offset 0x1C */
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unsigned int resv2;
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unsigned int tptc0clkctrl; /* offset 0x24 */
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unsigned int emifclkctrl; /* offset 0x28 */
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unsigned int ocmcramclkctrl; /* offset 0x2c */
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unsigned int gpmcclkctrl; /* offset 0x30 */
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unsigned int mcasp0clkctrl; /* offset 0x34 */
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unsigned int uart5clkctrl; /* offset 0x38 */
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unsigned int mmc0clkctrl; /* offset 0x3C */
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unsigned int elmclkctrl; /* offset 0x40 */
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unsigned int i2c2clkctrl; /* offset 0x44 */
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unsigned int i2c1clkctrl; /* offset 0x48 */
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unsigned int spi0clkctrl; /* offset 0x4C */
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unsigned int spi1clkctrl; /* offset 0x50 */
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unsigned int resv3[3];
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unsigned int l4lsclkctrl; /* offset 0x60 */
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unsigned int l4fwclkctrl; /* offset 0x64 */
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unsigned int mcasp1clkctrl; /* offset 0x68 */
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unsigned int uart1clkctrl; /* offset 0x6C */
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unsigned int uart2clkctrl; /* offset 0x70 */
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unsigned int uart3clkctrl; /* offset 0x74 */
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unsigned int uart4clkctrl; /* offset 0x78 */
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unsigned int timer7clkctrl; /* offset 0x7C */
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unsigned int timer2clkctrl; /* offset 0x80 */
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unsigned int timer3clkctrl; /* offset 0x84 */
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unsigned int timer4clkctrl; /* offset 0x88 */
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unsigned int resv4[8];
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unsigned int gpio1clkctrl; /* offset 0xAC */
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unsigned int gpio2clkctrl; /* offset 0xB0 */
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unsigned int gpio3clkctrl; /* offset 0xB4 */
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unsigned int resv5;
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unsigned int tpccclkctrl; /* offset 0xBC */
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unsigned int dcan0clkctrl; /* offset 0xC0 */
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unsigned int dcan1clkctrl; /* offset 0xC4 */
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unsigned int resv6[2];
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unsigned int emiffwclkctrl; /* offset 0xD0 */
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unsigned int resv7[2];
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unsigned int l3instrclkctrl; /* offset 0xDC */
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unsigned int l3clkctrl; /* Offset 0xE0 */
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unsigned int resv8[4];
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unsigned int mmc1clkctrl; /* offset 0xF4 */
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unsigned int mmc2clkctrl; /* offset 0xF8 */
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unsigned int resv9[8];
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unsigned int l4hsclkstctrl; /* offset 0x11C */
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unsigned int l4hsclkctrl; /* offset 0x120 */
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unsigned int resv10[8];
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unsigned int cpswclkstctrl; /* offset 0x144 */
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};
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/* Encapsulating Display pll registers */
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struct cm_dpll {
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unsigned int resv1[2];
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unsigned int clktimer2clk; /* offset 0x08 */
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};
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/* Watchdog timer registers */
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struct wd_timer {
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unsigned int resv1[4];
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unsigned int wdtwdsc; /* offset 0x010 */
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unsigned int wdtwdst; /* offset 0x014 */
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unsigned int wdtwisr; /* offset 0x018 */
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unsigned int wdtwier; /* offset 0x01C */
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unsigned int wdtwwer; /* offset 0x020 */
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unsigned int wdtwclr; /* offset 0x024 */
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unsigned int wdtwcrr; /* offset 0x028 */
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unsigned int wdtwldr; /* offset 0x02C */
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unsigned int wdtwtgr; /* offset 0x030 */
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unsigned int wdtwwps; /* offset 0x034 */
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unsigned int resv2[3];
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unsigned int wdtwdly; /* offset 0x044 */
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unsigned int wdtwspr; /* offset 0x048 */
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unsigned int resv3[1];
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unsigned int wdtwqeoi; /* offset 0x050 */
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unsigned int wdtwqstar; /* offset 0x054 */
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unsigned int wdtwqsta; /* offset 0x058 */
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unsigned int wdtwqens; /* offset 0x05C */
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unsigned int wdtwqenc; /* offset 0x060 */
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unsigned int resv4[39];
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unsigned int wdt_unfr; /* offset 0x100 */
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};
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/* Timer 32 bit registers */
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struct gptimer {
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unsigned int tidr; /* offset 0x00 */
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unsigned char res1[12];
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unsigned int tiocp_cfg; /* offset 0x10 */
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unsigned char res2[12];
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unsigned int tier; /* offset 0x20 */
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unsigned int tistatr; /* offset 0x24 */
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unsigned int tistat; /* offset 0x28 */
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unsigned int tisr; /* offset 0x2c */
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unsigned int tcicr; /* offset 0x30 */
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unsigned int twer; /* offset 0x34 */
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unsigned int tclr; /* offset 0x38 */
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unsigned int tcrr; /* offset 0x3c */
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unsigned int tldr; /* offset 0x40 */
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unsigned int ttgr; /* offset 0x44 */
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unsigned int twpc; /* offset 0x48 */
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unsigned int tmar; /* offset 0x4c */
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unsigned int tcar1; /* offset 0x50 */
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unsigned int tscir; /* offset 0x54 */
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unsigned int tcar2; /* offset 0x58 */
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};
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/* UART Registers */
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struct uart_sys {
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unsigned int resv1[21];
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unsigned int uartsyscfg; /* offset 0x54 */
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unsigned int uartsyssts; /* offset 0x58 */
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};
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/* VTP Registers */
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struct vtp_reg {
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unsigned int vtp0ctrlreg;
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};
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/* Control Status Register */
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struct ctrl_stat {
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unsigned int resv1[16];
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unsigned int statusreg; /* ofset 0x40 */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#endif /* _AM33XX_CPU_H */
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