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https://github.com/AsahiLinux/u-boot
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9675d92027
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <dm/device-internal.h>
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#include <linux/err.h>
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#define CLINT_MTIME_OFFSET 0xbff8
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#define ACLINT_MTIME_OFFSET 0
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/* mtime register */
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#define MTIME_REG(base, offset) ((ulong)(base) + (offset))
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static u64 notrace riscv_aclint_timer_get_count(struct udevice *dev)
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{
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return readq((void __iomem *)MTIME_REG(dev_get_priv(dev),
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dev_get_driver_data(dev)));
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}
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#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
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/**
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* timer_early_get_rate() - Get the timer rate before driver model
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*/
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unsigned long notrace timer_early_get_rate(void)
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{
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return RISCV_MMODE_TIMER_FREQ;
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}
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/**
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* timer_early_get_count() - Get the timer count before driver model
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*
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*/
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u64 notrace timer_early_get_count(void)
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{
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return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
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RISCV_MMODE_TIMEROFF));
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}
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#endif
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static const struct timer_ops riscv_aclint_timer_ops = {
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.get_count = riscv_aclint_timer_get_count,
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};
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static int riscv_aclint_timer_probe(struct udevice *dev)
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{
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dev_set_priv(dev, dev_read_addr_ptr(dev));
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if (!dev_get_priv(dev))
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return -EINVAL;
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return timer_timebase_fallback(dev);
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}
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static const struct udevice_id riscv_aclint_timer_ids[] = {
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{ .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET },
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{ .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET },
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{ .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET },
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{ }
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};
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U_BOOT_DRIVER(riscv_aclint_timer) = {
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.name = "riscv_aclint_timer",
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.id = UCLASS_TIMER,
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.of_match = riscv_aclint_timer_ids,
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.probe = riscv_aclint_timer_probe,
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.ops = &riscv_aclint_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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