mirror of
https://github.com/AsahiLinux/u-boot
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c733fe91e4
[upstream of vendor commit 19a96f7c40a8fc1d0a6546ac2418d966e5840a99] The Clearfog devices have only one SDHC device. This is either eMMC if it is populated on the SOM or SDHC if not. The Linux device tree assumes the SDHC case. Detect if the device is an eMMC and fixup the device-tree so it will be detected by Linux. Ported from vendor repo at https://github.com/SolidRun/u-boot Signed-off-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
296 lines
8.2 KiB
C
296 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <env.h>
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#include <i2c.h>
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#include <init.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <mmc.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include "../common/tlv_data.h"
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#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
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#include <../serdes/a38x/high_speed_env_spec.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-15t1-clearfog"
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*/
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#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
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#define BOARD_GPP_OUT_ENA_MID 0xffffffff
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#define BOARD_GPP_OUT_VAL_LOW 0x0
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#define BOARD_GPP_OUT_VAL_MID 0x0
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#define BOARD_GPP_POL_LOW 0x0
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#define BOARD_GPP_POL_MID 0x0
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static struct tlv_data cf_tlv_data;
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static void cf_read_tlv_data(void)
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{
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static bool read_once;
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if (read_once)
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return;
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read_once = true;
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read_tlv_data(&cf_tlv_data);
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}
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/* The starting board_serdes_map reflects original Clearfog Pro usage */
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static struct serdes_map board_serdes_map[] = {
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{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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};
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void config_cfbase_serdes_map(void)
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{
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board_serdes_map[4].serdes_type = USB3_HOST0;
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board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
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board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
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}
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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{
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cf_read_tlv_data();
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/* Apply build configuration options before runtime configuration */
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if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB))
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board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS;
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if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA)) {
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board_serdes_map[4].serdes_type = SATA2;
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board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS;
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board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
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board_serdes_map[4].swap_rx = 1;
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}
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if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) {
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board_serdes_map[2].serdes_type = SATA1;
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board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
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board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
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board_serdes_map[2].swap_rx = 1;
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}
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/* Apply runtime detection changes */
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if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
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board_serdes_map[0].serdes_type = PEX0;
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board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
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board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
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} else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) {
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/* handle recognized product as noop, no adjustment required */
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} else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
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config_cfbase_serdes_map();
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} else {
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/*
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* Fallback to static default. EEPROM TLV support is not
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* enabled, runtime detection failed, hardware support is not
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* present, EEPROM is corrupt, or an unrecognized product name
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* is present.
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*/
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if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM))
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puts("EEPROM TLV detection failed: ");
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puts("Using static config for ");
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if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {
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puts("Clearfog Base.\n");
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config_cfbase_serdes_map();
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} else {
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puts("Clearfog Pro.\n");
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}
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}
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*serdes_map_array = board_serdes_map;
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*count = ARRAY_SIZE(board_serdes_map);
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return 0;
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}
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/*
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* Define the DDR layout / topology here in the board file. This will
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* be used by the DDR3 init code in the SPL U-Boot version to configure
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* the DDR3 controller.
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*/
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static struct mv_ddr_topology_map board_topology_map = {
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1600K, /* speed_bin */
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MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
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MV_DDR_DIE_CAP_4GBIT, /* mem_size */
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MV_DDR_FREQ_800, /* frequency */
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0, 0, /* cas_wl cas_l */
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MV_DDR_TEMP_LOW, /* temperature */
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MV_DDR_TIM_DEFAULT} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ {0} }, /* electrical configuration */
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{0,}, /* electrical parameters */
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0, /* ODT configuration */
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0x3, /* clock enable mask */
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};
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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struct if_params *ifp = &board_topology_map.interface_params[0];
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cf_read_tlv_data();
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switch (cf_tlv_data.ram_size) {
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case 4:
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default:
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ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
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break;
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case 8:
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ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
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break;
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}
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x11111111, MVEBU_MPP_BASE + 0x00);
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writel(0x11111111, MVEBU_MPP_BASE + 0x04);
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writel(0x10400011, MVEBU_MPP_BASE + 0x08);
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writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
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writel(0x44400002, MVEBU_MPP_BASE + 0x10);
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writel(0x41144004, MVEBU_MPP_BASE + 0x14);
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writel(0x40333333, MVEBU_MPP_BASE + 0x18);
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writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
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/* Set GPP Out value */
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writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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/* Set GPP Polarity */
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writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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/* Toggle GPIO41 to reset onboard switch and phy */
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clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
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clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
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/* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
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clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
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clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
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mdelay(1);
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setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
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setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
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mdelay(10);
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return 0;
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}
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int checkboard(void)
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{
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char *board = "Clearfog Pro";
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if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
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board = "Clearfog Base";
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cf_read_tlv_data();
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if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
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board = cf_tlv_data.tlv_product_name[0];
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printf("Board: SolidRun %s", board);
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if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
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printf(", %s", cf_tlv_data.tlv_product_name[1]);
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puts("\n");
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return 0;
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}
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int board_eth_init(struct bd_info *bis)
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{
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cpu_eth_init(bis); /* Built in controller(s) come first */
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return pci_eth_init(bis);
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}
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int board_late_init(void)
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{
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if (env_get("fdtfile"))
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return 0;
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cf_read_tlv_data();
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if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
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env_set("fdtfile", "armada-388-clearfog-base.dtb");
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else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
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env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
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else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
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env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");
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else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
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env_set("fdtfile", "armada-388-clearfog-base.dtb");
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else
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env_set("fdtfile", "armada-388-clearfog-pro.dtb");
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return 0;
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}
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static bool has_emmc(void)
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{
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struct mmc *mmc;
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mmc = find_mmc_device(0);
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if (!mmc)
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return 0;
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return (!mmc_init(mmc) && IS_MMC(mmc)) ? true : false;
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}
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/*
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* The Clearfog devices have only one SDHC device. This is either eMMC
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* if it is populated on the SOM or SDHC if not. The Linux device tree
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* assumes the SDHC case. Detect if the device is an eMMC and fixup the
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* device-tree, so that it will be detected by Linux.
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*/
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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int node;
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if (has_emmc()) {
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node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-380-sdhci");
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if (node < 0)
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return 0; /* Unexpected eMMC device; patching not supported */
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puts("Patching FDT so that eMMC is detected by OS\n");
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return fdt_setprop_empty(blob, node, "non-removable");
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}
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return 0;
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}
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