mirror of
https://github.com/AsahiLinux/u-boot
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2ff17d2f74
Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit for i.MX8M" breaks the 64 bits CAAM. Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64), to adapt and not break 64 bits CAAM support, add a new config CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t". This config is default enabled when CONFIG_PHYS_64BIT is set except for iMX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
745 lines
18 KiB
C
745 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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* Based on CAAM driver in drivers/crypto/caam in Linux
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <linux/kernel.h>
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#include <log.h>
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#include <malloc.h>
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#include "fsl_sec.h"
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#include "jr.h"
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#include "jobdesc.h"
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#include "desc_constr.h"
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#include <time.h>
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#include <asm/cache.h>
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#ifdef CONFIG_FSL_CORENET
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#include <asm/cache.h>
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#include <asm/fsl_pamu.h>
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#endif
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#include <dm/lists.h>
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#include <linux/delay.h>
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#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
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#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
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uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
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0,
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#if defined(CONFIG_ARCH_C29X)
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CONFIG_SYS_FSL_SEC_IDX_OFFSET,
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2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
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#endif
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};
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#define SEC_ADDR(idx) \
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(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
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#define SEC_JR0_ADDR(idx) \
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(ulong)(SEC_ADDR(idx) + \
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(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
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struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
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static inline void start_jr0(uint8_t sec_idx)
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{
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ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
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u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
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u32 scfgr = sec_in32(&sec->scfgr);
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if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
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/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
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* VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
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*/
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if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
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(scfgr & SEC_SCFGR_VIRT_EN))
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sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
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} else {
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/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
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if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
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sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
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}
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}
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static inline void jr_reset_liodn(uint8_t sec_idx)
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{
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ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
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sec_out32(&sec->jrliodnr[0].ls, 0);
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}
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static inline void jr_disable_irq(uint8_t sec_idx)
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{
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struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
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uint32_t jrcfg = sec_in32(®s->jrcfg1);
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jrcfg = jrcfg | JR_INTMASK;
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sec_out32(®s->jrcfg1, jrcfg);
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}
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static void jr_initregs(uint8_t sec_idx)
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{
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struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
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struct jobring *jr = &jr0[sec_idx];
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caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
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caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
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#ifdef CONFIG_CAAM_64BIT
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sec_out32(®s->irba_h, ip_base >> 32);
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#else
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sec_out32(®s->irba_h, 0x0);
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#endif
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sec_out32(®s->irba_l, (uint32_t)ip_base);
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#ifdef CONFIG_CAAM_64BIT
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sec_out32(®s->orba_h, op_base >> 32);
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#else
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sec_out32(®s->orba_h, 0x0);
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#endif
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sec_out32(®s->orba_l, (uint32_t)op_base);
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sec_out32(®s->ors, JR_SIZE);
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sec_out32(®s->irs, JR_SIZE);
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if (!jr->irq)
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jr_disable_irq(sec_idx);
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}
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static int jr_init(uint8_t sec_idx)
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{
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struct jobring *jr = &jr0[sec_idx];
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memset(jr, 0, sizeof(struct jobring));
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jr->jq_id = DEFAULT_JR_ID;
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jr->irq = DEFAULT_IRQ;
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#ifdef CONFIG_FSL_CORENET
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jr->liodn = DEFAULT_JR_LIODN;
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#endif
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jr->size = JR_SIZE;
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jr->input_ring = (caam_dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
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JR_SIZE * sizeof(caam_dma_addr_t));
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if (!jr->input_ring)
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return -1;
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jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
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ARCH_DMA_MINALIGN);
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jr->output_ring =
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(struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
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if (!jr->output_ring)
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return -1;
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memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
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memset(jr->output_ring, 0, jr->op_size);
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start_jr0(sec_idx);
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jr_initregs(sec_idx);
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return 0;
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}
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static int jr_sw_cleanup(uint8_t sec_idx)
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{
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struct jobring *jr = &jr0[sec_idx];
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jr->head = 0;
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jr->tail = 0;
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jr->read_idx = 0;
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jr->write_idx = 0;
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memset(jr->info, 0, sizeof(jr->info));
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memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
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memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
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return 0;
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}
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static int jr_hw_reset(uint8_t sec_idx)
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{
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struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
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uint32_t timeout = 100000;
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uint32_t jrint, jrcr;
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sec_out32(®s->jrcr, JRCR_RESET);
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do {
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jrint = sec_in32(®s->jrint);
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} while (((jrint & JRINT_ERR_HALT_MASK) ==
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JRINT_ERR_HALT_INPROGRESS) && --timeout);
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jrint = sec_in32(®s->jrint);
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if (((jrint & JRINT_ERR_HALT_MASK) !=
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JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
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return -1;
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timeout = 100000;
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sec_out32(®s->jrcr, JRCR_RESET);
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do {
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jrcr = sec_in32(®s->jrcr);
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} while ((jrcr & JRCR_RESET) && --timeout);
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if (timeout == 0)
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return -1;
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return 0;
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}
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/* -1 --- error, can't enqueue -- no space available */
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static int jr_enqueue(uint32_t *desc_addr,
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void (*callback)(uint32_t status, void *arg),
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void *arg, uint8_t sec_idx)
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{
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struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
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struct jobring *jr = &jr0[sec_idx];
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int head = jr->head;
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uint32_t desc_word;
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int length = desc_len(desc_addr);
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int i;
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#ifdef CONFIG_CAAM_64BIT
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uint32_t *addr_hi, *addr_lo;
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#endif
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/* The descriptor must be submitted to SEC block as per endianness
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* of the SEC Block.
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* So, if the endianness of Core and SEC block is different, each word
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* of the descriptor will be byte-swapped.
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*/
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for (i = 0; i < length; i++) {
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desc_word = desc_addr[i];
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sec_out32((uint32_t *)&desc_addr[i], desc_word);
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}
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caam_dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
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jr->info[head].desc_phys_addr = desc_phys_addr;
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jr->info[head].callback = (void *)callback;
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jr->info[head].arg = arg;
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jr->info[head].op_done = 0;
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unsigned long start = (unsigned long)&jr->info[head] &
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~(ARCH_DMA_MINALIGN - 1);
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unsigned long end = ALIGN((unsigned long)&jr->info[head] +
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sizeof(struct jr_info), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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#ifdef CONFIG_CAAM_64BIT
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/* Write the 64 bit Descriptor address on Input Ring.
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* The 32 bit hign and low part of the address will
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* depend on endianness of SEC block.
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*/
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#ifdef CONFIG_SYS_FSL_SEC_LE
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addr_lo = (uint32_t *)(&jr->input_ring[head]);
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addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
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#elif defined(CONFIG_SYS_FSL_SEC_BE)
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addr_hi = (uint32_t *)(&jr->input_ring[head]);
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addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
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#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
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sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
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sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
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#else
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/* Write the 32 bit Descriptor address on Input Ring. */
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sec_out32(&jr->input_ring[head], desc_phys_addr);
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#endif /* ifdef CONFIG_CAAM_64BIT */
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start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
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end = ALIGN((unsigned long)&jr->input_ring[head] +
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sizeof(caam_dma_addr_t), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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jr->head = (head + 1) & (jr->size - 1);
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/* Invalidate output ring */
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start = (unsigned long)jr->output_ring &
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~(ARCH_DMA_MINALIGN - 1);
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end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
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ARCH_DMA_MINALIGN);
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invalidate_dcache_range(start, end);
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sec_out32(®s->irja, 1);
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return 0;
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}
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static int jr_dequeue(int sec_idx)
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{
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struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
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struct jobring *jr = &jr0[sec_idx];
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int head = jr->head;
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int tail = jr->tail;
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int idx, i, found;
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void (*callback)(uint32_t status, void *arg);
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void *arg = NULL;
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#ifdef CONFIG_CAAM_64BIT
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uint32_t *addr_hi, *addr_lo;
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#else
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uint32_t *addr;
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#endif
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while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail,
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jr->size)) {
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found = 0;
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caam_dma_addr_t op_desc;
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#ifdef CONFIG_CAAM_64BIT
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/* Read the 64 bit Descriptor address from Output Ring.
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* The 32 bit hign and low part of the address will
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* depend on endianness of SEC block.
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*/
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#ifdef CONFIG_SYS_FSL_SEC_LE
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addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
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addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
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#elif defined(CONFIG_SYS_FSL_SEC_BE)
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addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
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addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
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#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
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op_desc = ((u64)sec_in32(addr_hi) << 32) |
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((u64)sec_in32(addr_lo));
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#else
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/* Read the 32 bit Descriptor address from Output Ring. */
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addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
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op_desc = sec_in32(addr);
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#endif /* ifdef CONFIG_CAAM_64BIT */
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uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
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for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
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idx = (tail + i) & (jr->size - 1);
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if (op_desc == jr->info[idx].desc_phys_addr) {
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found = 1;
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break;
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}
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}
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/* Error condition if match not found */
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if (!found)
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return -1;
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jr->info[idx].op_done = 1;
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callback = (void *)jr->info[idx].callback;
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arg = jr->info[idx].arg;
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/* When the job on tail idx gets done, increment
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* tail till the point where job completed out of oredr has
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* been taken into account
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*/
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if (idx == tail)
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do {
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tail = (tail + 1) & (jr->size - 1);
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} while (jr->info[tail].op_done);
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jr->tail = tail;
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jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
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sec_out32(®s->orjr, 1);
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jr->info[idx].op_done = 0;
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callback(status, arg);
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}
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return 0;
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}
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static void desc_done(uint32_t status, void *arg)
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{
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struct result *x = arg;
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x->status = status;
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#ifndef CONFIG_SPL_BUILD
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caam_jr_strstatus(status);
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#endif
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x->done = 1;
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}
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static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
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{
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unsigned long long timeval = 0;
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unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
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struct result op;
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int ret = 0;
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memset(&op, 0, sizeof(op));
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ret = jr_enqueue(desc, desc_done, &op, sec_idx);
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if (ret) {
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debug("Error in SEC enq\n");
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ret = JQ_ENQ_ERR;
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goto out;
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}
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while (op.done != 1) {
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udelay(1);
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timeval += 1;
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ret = jr_dequeue(sec_idx);
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if (ret) {
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debug("Error in SEC deq\n");
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ret = JQ_DEQ_ERR;
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goto out;
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}
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if (timeval > timeout) {
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debug("SEC Dequeue timed out\n");
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ret = JQ_DEQ_TO_ERR;
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goto out;
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}
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}
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if (op.status) {
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debug("Error %x\n", op.status);
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ret = op.status;
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}
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out:
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return ret;
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}
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int run_descriptor_jr(uint32_t *desc)
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{
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return run_descriptor_jr_idx(desc, 0);
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}
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static inline int jr_reset_sec(uint8_t sec_idx)
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{
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if (jr_hw_reset(sec_idx) < 0)
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return -1;
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/* Clean up the jobring structure maintained by software */
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jr_sw_cleanup(sec_idx);
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return 0;
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}
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int jr_reset(void)
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{
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return jr_reset_sec(0);
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}
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static inline int sec_reset_idx(uint8_t sec_idx)
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{
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ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
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uint32_t mcfgr = sec_in32(&sec->mcfgr);
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uint32_t timeout = 100000;
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mcfgr |= MCFGR_SWRST;
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sec_out32(&sec->mcfgr, mcfgr);
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mcfgr |= MCFGR_DMA_RST;
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sec_out32(&sec->mcfgr, mcfgr);
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do {
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mcfgr = sec_in32(&sec->mcfgr);
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} while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
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if (timeout == 0)
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return -1;
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timeout = 100000;
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do {
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mcfgr = sec_in32(&sec->mcfgr);
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} while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
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if (timeout == 0)
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return -1;
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return 0;
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}
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int sec_reset(void)
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{
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return sec_reset_idx(0);
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}
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#ifndef CONFIG_SPL_BUILD
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static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
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{
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u32 *desc;
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int sh_idx, ret = 0;
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int desc_size = ALIGN(sizeof(u32) * 2, ARCH_DMA_MINALIGN);
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desc = memalign(ARCH_DMA_MINALIGN, desc_size);
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if (!desc) {
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debug("cannot allocate RNG init descriptor memory\n");
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return -ENOMEM;
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}
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for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
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/*
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* If the corresponding bit is set, then it means the state
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* handle was initialized by us, and thus it needs to be
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* deinitialized as well
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*/
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|
|
if (state_handle_mask & RDSTA_IF(sh_idx)) {
|
|
/*
|
|
* Create the descriptor for deinstantating this state
|
|
* handle.
|
|
*/
|
|
inline_cnstr_jobdesc_rng_deinstantiation(desc, sh_idx);
|
|
flush_dcache_range((unsigned long)desc,
|
|
(unsigned long)desc + desc_size);
|
|
|
|
ret = run_descriptor_jr_idx(desc, sec_idx);
|
|
if (ret) {
|
|
printf("SEC%u: RNG4 SH%d deinstantiation failed with error 0x%x\n",
|
|
sec_idx, sh_idx, ret);
|
|
ret = -EIO;
|
|
break;
|
|
}
|
|
|
|
printf("SEC%u: Deinstantiated RNG4 SH%d\n",
|
|
sec_idx, sh_idx);
|
|
}
|
|
}
|
|
|
|
free(desc);
|
|
return ret;
|
|
}
|
|
|
|
static int instantiate_rng(u8 sec_idx, int gen_sk)
|
|
{
|
|
u32 *desc;
|
|
u32 rdsta_val;
|
|
int ret = 0, sh_idx, size;
|
|
ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
|
|
struct rng4tst __iomem *rng =
|
|
(struct rng4tst __iomem *)&sec->rng;
|
|
|
|
desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
|
|
if (!desc) {
|
|
printf("cannot allocate RNG init descriptor memory\n");
|
|
return -1;
|
|
}
|
|
|
|
for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
|
|
/*
|
|
* If the corresponding bit is set, this state handle
|
|
* was initialized by somebody else, so it's left alone.
|
|
*/
|
|
rdsta_val = sec_in32(&rng->rdsta);
|
|
if (rdsta_val & (RDSTA_IF(sh_idx))) {
|
|
if (rdsta_val & RDSTA_PR(sh_idx))
|
|
continue;
|
|
|
|
printf("SEC%u: RNG4 SH%d was instantiated w/o prediction resistance. Tearing it down\n",
|
|
sec_idx, sh_idx);
|
|
|
|
ret = deinstantiate_rng(sec_idx, RDSTA_IF(sh_idx));
|
|
if (ret)
|
|
break;
|
|
}
|
|
|
|
inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk);
|
|
size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
|
|
flush_dcache_range((unsigned long)desc,
|
|
(unsigned long)desc + size);
|
|
|
|
ret = run_descriptor_jr_idx(desc, sec_idx);
|
|
|
|
if (ret)
|
|
printf("SEC%u: RNG4 SH%d instantiation failed with error 0x%x\n",
|
|
sec_idx, sh_idx, ret);
|
|
|
|
rdsta_val = sec_in32(&rng->rdsta);
|
|
if (!(rdsta_val & RDSTA_IF(sh_idx))) {
|
|
free(desc);
|
|
return -1;
|
|
}
|
|
|
|
memset(desc, 0, sizeof(uint32_t) * 6);
|
|
}
|
|
|
|
free(desc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static u8 get_rng_vid(uint8_t sec_idx)
|
|
{
|
|
ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
|
|
u8 vid;
|
|
|
|
if (caam_get_era() < 10) {
|
|
vid = (sec_in32(&sec->chavid_ls) & SEC_CHAVID_RNG_LS_MASK)
|
|
>> SEC_CHAVID_LS_RNG_SHIFT;
|
|
} else {
|
|
vid = (sec_in32(&sec->vreg.rng) & CHA_VER_VID_MASK)
|
|
>> CHA_VER_VID_SHIFT;
|
|
}
|
|
|
|
return vid;
|
|
}
|
|
|
|
/*
|
|
* By default, the TRNG runs for 200 clocks per sample;
|
|
* 1200 clocks per sample generates better entropy.
|
|
*/
|
|
static void kick_trng(int ent_delay, uint8_t sec_idx)
|
|
{
|
|
ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
|
|
struct rng4tst __iomem *rng =
|
|
(struct rng4tst __iomem *)&sec->rng;
|
|
u32 val;
|
|
|
|
/* put RNG4 into program mode */
|
|
sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
|
|
/* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
|
|
* length (in system clocks) of each Entropy sample taken
|
|
* */
|
|
val = sec_in32(&rng->rtsdctl);
|
|
val = (val & ~RTSDCTL_ENT_DLY_MASK) |
|
|
(ent_delay << RTSDCTL_ENT_DLY_SHIFT);
|
|
sec_out32(&rng->rtsdctl, val);
|
|
/* min. freq. count, equal to 1/4 of the entropy sample length */
|
|
sec_out32(&rng->rtfreqmin, ent_delay >> 2);
|
|
/* disable maximum frequency count */
|
|
sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
|
|
/*
|
|
* select raw sampling in both entropy shifter
|
|
* and statistical checker
|
|
*/
|
|
sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
|
|
/* put RNG4 into run mode */
|
|
sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
|
|
}
|
|
|
|
static int rng_init(uint8_t sec_idx)
|
|
{
|
|
int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
|
|
ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
|
|
struct rng4tst __iomem *rng =
|
|
(struct rng4tst __iomem *)&sec->rng;
|
|
u32 inst_handles;
|
|
|
|
gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN);
|
|
do {
|
|
inst_handles = sec_in32(&rng->rdsta) & RDSTA_MASK;
|
|
|
|
/*
|
|
* If either of the SH's were instantiated by somebody else
|
|
* then it is assumed that the entropy
|
|
* parameters are properly set and thus the function
|
|
* setting these (kick_trng(...)) is skipped.
|
|
* Also, if a handle was instantiated, do not change
|
|
* the TRNG parameters.
|
|
*/
|
|
if (!inst_handles) {
|
|
kick_trng(ent_delay, sec_idx);
|
|
ent_delay += 400;
|
|
}
|
|
/*
|
|
* if instantiate_rng(...) fails, the loop will rerun
|
|
* and the kick_trng(...) function will modfiy the
|
|
* upper and lower limits of the entropy sampling
|
|
* interval, leading to a sucessful initialization of
|
|
* the RNG.
|
|
*/
|
|
ret = instantiate_rng(sec_idx, gen_sk);
|
|
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
|
|
if (ret) {
|
|
printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
|
|
return ret;
|
|
}
|
|
|
|
/* Enable RDB bit so that RNG works faster */
|
|
sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
int sec_init_idx(uint8_t sec_idx)
|
|
{
|
|
ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
|
|
uint32_t mcr = sec_in32(&sec->mcfgr);
|
|
int ret = 0;
|
|
|
|
#ifdef CONFIG_FSL_CORENET
|
|
uint32_t liodnr;
|
|
uint32_t liodn_ns;
|
|
uint32_t liodn_s;
|
|
#endif
|
|
|
|
if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
|
|
printf("SEC%u: initialization failed\n", sec_idx);
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Modifying CAAM Read/Write Attributes
|
|
* For LS2080A
|
|
* For AXI Write - Cacheable, Write Back, Write allocate
|
|
* For AXI Read - Cacheable, Read allocate
|
|
* Only For LS2080a, to solve CAAM coherency issues
|
|
*/
|
|
#ifdef CONFIG_ARCH_LS2080A
|
|
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
|
|
mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
|
|
#else
|
|
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
|
|
#endif
|
|
|
|
#ifdef CONFIG_CAAM_64BIT
|
|
mcr |= (1 << MCFGR_PS_SHIFT);
|
|
#endif
|
|
sec_out32(&sec->mcfgr, mcr);
|
|
|
|
#ifdef CONFIG_FSL_CORENET
|
|
#ifdef CONFIG_SPL_BUILD
|
|
/*
|
|
* For SPL Build, Set the Liodns in SEC JR0 for
|
|
* creating PAMU entries corresponding to these.
|
|
* For normal build, these are set in set_liodns().
|
|
*/
|
|
liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
|
|
liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
|
|
|
|
liodnr = sec_in32(&sec->jrliodnr[0].ls) &
|
|
~(JRNSLIODN_MASK | JRSLIODN_MASK);
|
|
liodnr = liodnr |
|
|
(liodn_ns << JRNSLIODN_SHIFT) |
|
|
(liodn_s << JRSLIODN_SHIFT);
|
|
sec_out32(&sec->jrliodnr[0].ls, liodnr);
|
|
#else
|
|
liodnr = sec_in32(&sec->jrliodnr[0].ls);
|
|
liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
|
|
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
|
|
#endif
|
|
#endif
|
|
|
|
ret = jr_init(sec_idx);
|
|
if (ret < 0) {
|
|
printf("SEC%u: initialization failed\n", sec_idx);
|
|
return -1;
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_CORENET
|
|
ret = sec_config_pamu_table(liodn_ns, liodn_s);
|
|
if (ret < 0)
|
|
return -1;
|
|
|
|
pamu_enable();
|
|
#endif
|
|
#ifndef CONFIG_SPL_BUILD
|
|
if (get_rng_vid(sec_idx) >= 4) {
|
|
if (rng_init(sec_idx) < 0) {
|
|
printf("SEC%u: RNG instantiation failed\n", sec_idx);
|
|
return -1;
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_DM_RNG)) {
|
|
ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
|
|
NULL);
|
|
if (ret)
|
|
printf("Couldn't bind rng driver (%d)\n", ret);
|
|
}
|
|
|
|
printf("SEC%u: RNG instantiated\n", sec_idx);
|
|
}
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
int sec_init(void)
|
|
{
|
|
return sec_init_idx(0);
|
|
}
|