mirror of
https://github.com/AsahiLinux/u-boot
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5c214bac46
All zynqmp boards have been already described via mdio node that's why also convert the rest of the boards. With using mdio node there is an option to add reset property for the whole mdio bus which is reflected by 's/phy-reset-gpios/reset-gpios/g' for some boards. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.simek@amd.com
563 lines
9.6 KiB
Text
563 lines
9.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP zc1751-xm016-dc2
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*
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* (C) Copyright 2015 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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/ {
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model = "ZynqMP zc1751-xm016-dc2 RevA";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem2;
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i2c0 = &i2c0;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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spi0 = &spi0;
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spi1 = &spi1;
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usb0 = &usb1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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};
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&can0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can0_default>;
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};
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&can1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1_default>;
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gem2 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem2_default>;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@5 {
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reg = <5>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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};
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&gpio {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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pinctrl-1 = <&pinctrl_i2c0_gpio>;
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scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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tca6416_u26: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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/* IRQ not connected */
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};
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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&nand0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand0_default>;
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arasan,has-mdma;
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nand@0 {
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reg = <0x0>;
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#address-cells = <0x2>;
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#size-cells = <0x1>;
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nand-ecc-mode = "soft";
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nand-ecc-algo = "bch";
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nand-rb = <0>;
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label = "main-storage-0";
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nand-ecc-step-size = <1024>;
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nand-ecc-strength = <24>;
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nand-on-flash-bbt;
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partition@0 { /* for testing purpose */
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label = "nand-fsbl-uboot";
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reg = <0x0 0x0 0x400000>;
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};
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partition@1 { /* for testing purpose */
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label = "nand-linux";
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reg = <0x0 0x400000 0x1400000>;
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};
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partition@2 { /* for testing purpose */
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label = "nand-device-tree";
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reg = <0x0 0x1800000 0x400000>;
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};
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partition@3 { /* for testing purpose */
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label = "nand-rootfs";
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reg = <0x0 0x1c00000 0x1400000>;
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};
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partition@4 { /* for testing purpose */
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label = "nand-bitstream";
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reg = <0x0 0x3000000 0x400000>;
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};
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partition@5 { /* for testing purpose */
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label = "nand-misc";
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reg = <0x0 0x3400000 0xfcc00000>;
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};
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};
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nand@1 {
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reg = <0x1>;
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#address-cells = <0x2>;
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#size-cells = <0x1>;
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nand-ecc-mode = "soft";
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nand-ecc-algo = "bch";
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nand-rb = <0>;
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label = "main-storage-1";
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nand-ecc-step-size = <1024>;
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nand-ecc-strength = <24>;
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nand-on-flash-bbt;
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partition@0 { /* for testing purpose */
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label = "nand1-fsbl-uboot";
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reg = <0x0 0x0 0x400000>;
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};
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partition@1 { /* for testing purpose */
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label = "nand1-linux";
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reg = <0x0 0x400000 0x1400000>;
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};
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partition@2 { /* for testing purpose */
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label = "nand1-device-tree";
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reg = <0x0 0x1800000 0x400000>;
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};
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partition@3 { /* for testing purpose */
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label = "nand1-rootfs";
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reg = <0x0 0x1c00000 0x1400000>;
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};
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partition@4 { /* for testing purpose */
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label = "nand1-bitstream";
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reg = <0x0 0x3000000 0x400000>;
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};
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partition@5 { /* for testing purpose */
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label = "nand1-misc";
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reg = <0x0 0x3400000 0xfcc00000>;
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};
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};
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};
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&pinctrl0 {
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status = "okay";
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pinctrl_can0_default: can0-default {
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mux {
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function = "can0";
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groups = "can0_9_grp";
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};
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conf {
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groups = "can0_9_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO38";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO39";
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bias-disable;
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};
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};
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pinctrl_can1_default: can1-default {
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mux {
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function = "can1";
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groups = "can1_8_grp";
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};
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conf {
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groups = "can1_8_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO33";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO32";
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bias-disable;
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};
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};
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pinctrl_i2c0_default: i2c0-default {
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mux {
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groups = "i2c0_1_grp";
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function = "i2c0";
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};
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conf {
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groups = "i2c0_1_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c0_gpio: i2c0-gpio {
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mux {
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groups = "gpio0_6_grp", "gpio0_7_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_6_grp", "gpio0_7_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_uart0_default: uart0-default {
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mux {
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groups = "uart0_10_grp";
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function = "uart0";
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};
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conf {
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groups = "uart0_10_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO42";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO43";
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bias-disable;
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};
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};
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_10_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_10_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO41";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO40";
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bias-disable;
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};
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};
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pinctrl_usb1_default: usb1-default {
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mux {
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groups = "usb1_0_grp";
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function = "usb1";
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};
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conf {
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groups = "usb1_0_grp";
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO64", "MIO65", "MIO67";
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bias-high-impedance;
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drive-strength = <12>;
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slew-rate = <SLEW_RATE_FAST>;
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};
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conf-tx {
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pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
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"MIO72", "MIO73", "MIO74", "MIO75";
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bias-disable;
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drive-strength = <4>;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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};
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pinctrl_gem2_default: gem2-default {
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mux {
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function = "ethernet2";
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groups = "ethernet2_0_grp";
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};
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conf {
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groups = "ethernet2_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
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"MIO63";
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bias-high-impedance;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
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"MIO57";
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bias-disable;
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low-power-enable;
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};
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mux-mdio {
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function = "mdio2";
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groups = "mdio2_0_grp";
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};
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conf-mdio {
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groups = "mdio2_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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};
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pinctrl_nand0_default: nand0-default {
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mux {
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groups = "nand0_0_grp";
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function = "nand0";
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};
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conf {
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groups = "nand0_0_grp";
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bias-pull-up;
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};
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mux-ce {
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groups = "nand0_ce_0_grp";
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function = "nand0_ce";
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};
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conf-ce {
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groups = "nand0_ce_0_grp";
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bias-pull-up;
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};
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mux-rb {
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groups = "nand0_rb_0_grp";
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function = "nand0_rb";
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};
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conf-rb {
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groups = "nand0_rb_0_grp";
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bias-pull-up;
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};
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mux-dqs {
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groups = "nand0_dqs_0_grp";
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function = "nand0_dqs";
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};
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conf-dqs {
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groups = "nand0_dqs_0_grp";
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bias-pull-up;
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};
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};
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pinctrl_spi0_default: spi0-default {
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mux {
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groups = "spi0_0_grp";
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function = "spi0";
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};
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conf {
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groups = "spi0_0_grp";
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bias-disable;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux-cs {
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groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
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"spi0_ss_2_grp";
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function = "spi0_ss";
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};
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conf-cs {
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groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
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"spi0_ss_2_grp";
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bias-disable;
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};
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};
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pinctrl_spi1_default: spi1-default {
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mux {
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groups = "spi1_3_grp";
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function = "spi1";
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};
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conf {
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groups = "spi1_3_grp";
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bias-disable;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux-cs {
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groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
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"spi1_ss_11_grp";
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function = "spi1_ss";
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};
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conf-cs {
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groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
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"spi1_ss_11_grp";
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bias-disable;
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};
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};
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};
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&rtc {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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num-cs = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0_default>;
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spi0_flash0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "sst,sst25wf080", "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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partition@0 {
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label = "spi0-data";
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reg = <0x0 0x100000>;
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};
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};
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};
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&spi1 {
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status = "okay";
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num-cs = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1_default>;
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spi1_flash0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
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spi-max-frequency = <20000000>;
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reg = <0>;
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partition@0 {
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label = "spi1-data";
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reg = <0x0 0x84000>;
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};
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};
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};
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/* ULPI SMSC USB3320 */
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&usb1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1_default>;
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};
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&dwc3_1 {
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status = "okay";
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dr_mode = "host";
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};
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&uart0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0_default>;
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};
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&uart1 {
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status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1_default>;
|
|
};
|